JPS603031A - Information processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical field to which the invention pertains] This invention provides a method for combining an address condition and a data condition as a set.
The present invention relates to an information processing device that can interrupt a predetermined execution program.

[Prior art and its problems]

Under the conventional so-called stored program method,
In an information processing device that executes a program, a predetermined address condition ('1) is set so that the address condition At that point, running Programno,
There is one that has the function of increasing the middle level.

Here, as an address for the middle 1tli condition, there is a soenochiatre address or an itastore address for an instruction, but a program is programmed in a so-called multi-programming system-1 in which multiple solenograms are dynamically loaded and executed. In the information processing device that performs the execution of It is not possible to judge whether the L-resist is an erotic experience.

Therefore, the above address interrupting method (a-C) has the following problems because the middle tlji condition is the force for matching the address condition.

■ Under a multi-programming system, if processing is interrupted during the execution of a specific program program in area 1a above, the setting of one address does not necessarily mean that the target program program is in progress! ji しな、い. Therefore, it becomes necessary to check the status every time the process is interrupted and to repeatedly continue or interrupt the process until the target Progera J1 is completed.

■ Main memory 2. Under certain conditions, if you try to interrupt the process and analyze the data that changes dynamically, you will find yourself at the target! Until ε1 is reached, there are a large number of processing steps from data recognition to continuation and interruption of processing, and it takes about 1 hour.

[Purpose of the invention]

The present invention solves the problems of the prior art and provides an information processing device that can easily perform processing in a predetermined processing state of a program or system that can be requested. Let's take it as Iyo1.

[Key points of the invention]

The z1 feature of the present invention to achieve such an object is to execute an execution program rJ according to a predetermined address condition that has been set.
In an information processing device that has a function that can process 1111 programs, an address condition ('l) and a data condition setting T stage are set up, and these address conditions and data conditions (11-2-) are set. The suspension shall be effected upon the establishment of Article (2) 1.

[Embodiments of the invention]

Hereinafter, an example of a buoy according to the present invention will be explained with reference to the drawings.

11. It is a block diagram of the main part of the information processing device which can be used in this invention.

The processing device 30 includes a store address/data setting unit and a fetch address/data setting unit that determine the interrupt condition (/I), respective collation units that detect the establishment of the respective interrupt conditions for these, and ζ, It is provided with a complex condition determination section that logically converts the verification results from each verification section, checks whether the verification results match the set conditions, and generates an error message.

The Zunawa right store address/data setting section consists of a complex condition setter 1G and a store address/data condition setting register group 4, and a fetch address/data setting r.
)1) is composed of a composite condition setter 16 and a fetch address/data condition setting register group 10.

Here, store address/data condition setting register group 4
and 2, Sochia 1-I/S data condition setting register group 10, in combination with arbitrary execution-5' address and data in the above 1.1 device? The configuration is such that the number of jl & 1.1 can be set. For this reason, for example 31, store address/data condition setting register
The response and data are recorded as one river, which is 9, and each set is recorded as 1a, which is the response section Δ1.
→-Data Record 1a Part I) 1. A.I.Res. Part 1/)
)Δ2+data record 1. q portion 1) 2, -j' l-resistance storage portion Δ3→-data storage portion D3. ..., A1.1/S 1ki 1; I; Minute An 4 Data storage part [
) 11 and 6. In addition, in the fetch address/data row ear 1 setting/sister group 10, the address and data address are stored as IHll, and this one set is stored as address record 1, a part FΔII-
Data Record 1 Takubu U30 ■] 1.7 Flz Su Record 11 Part F
A2 ” Data record 1.?, ffB 37' OP
2. Address storage part FΔ3 + data storage IQ part OP3
,..., address record unique part FΔm-1 data record 1 (
Contains 7 parts OPm.

In addition, as a verification unit that detects the establishment of an interruption condition for the data (hereinafter referred to as store address value + data) at the store address value, the store address data condition is A determiner 5 and a store address/data condition logical variable register group 6 are numbered.In this case, fetch address value I=that address value, 1.i DJ data (hereinafter referred to as fetch address value) A fetch address/data condition determiner 11 and a 7-chia IS-less operation L--sicon condition logic variable register IY12 are provided as a collation unit for detecting the establishment of an interruption condition for the data (referred to as 10 data). .

These collation units then match the address value accessed by the execution program at any given time, the 4ftl data at that address (hereinafter referred to as address value + data), and the set rl + l folding condition (address value → - data). Compare the ratio axis.

The store address/data condition logical variable register 711' 6 and the fetch address/operation condition logical variable register group 12 store the store address/data condition (from the 71 determiner 5 and the fetch address/data condition determiner 11). It also plays the role of a so-called "flash" which stores established result signals indicating whether there is a match or mismatch as a result of each comparison.

Therefore, corresponding to the results of each collation, store address and data row Il'p[
i, the logical variable register Xl+χ2. X3.・・・
・,Xn, Fencia 1-less operation condition In the logical variable register group 12, logical variable registers Yl, Y
2. Y3. ..., has Ym.

The signals of the store address/data row (71) logic change register group 6 and the fetch address/operation condition logical variable register group 12 are sent to a complex row ear 1 judger which constitutes a compound condition judger that generates an interrupt signal, respectively. 1
8, which undergoes a predetermined logical conversion and is compared with the condition signal from the compound condition setter 16 at L-1. Part 1
1.1j As a result, when these match, an interrupt signal "bow" is generated in the interrupt signal cotton 20l2.

By the way, in the figure, 1 is the memory address/sister (MΔ
R), 2 is a memory data register (MDR), 7 is
An operation register (OPR), 3 is a store condition constant strobe signal line, and 8 is an address register connected to the memory address register 2 via the store address/data condition determiner 5. Data line 9 is
This is the first step in determining the fetch condition. Also, 1
3 and 14 are compound condition determination strobe signal lines, 15 is a condition setting signal line, and 19 is a match condition identification register.

Next, the overall operation of the information processing device 30 having the following configuration will be described.

First, the memory address register 1, the memory data register 2, the store condition determination strobe signal line 3, the operation register 7, and the phenol condition determination strobe signal line 9 are generally connected to the information processing word (ξ When the processing device (not shown) of the information processing device 30 reads data from the main storage device, the address value of the corresponding data is first read into the memory address register 1. accesses the main memory and writes the eft output data to memory data storage 2.Meanwhile, the instruction is transferred from the
When the fetch address 1 is sent to the memory address l/sled disk 1, the main memory is accessed, and the successive operation code F' (this light?11
In the first book, it is used to include this operation call l- in the concept of data) to the operation register 7.

In this way, predetermined data is obtained and predetermined processing is executed. Here, the strobe signal is sent to the store condition determination strobe signal line 3 when the store command is executed. The strobe signal is sent to i19 immediately after the processing of the 1, -, instruction is completed.

Now, the compound condition setter 16 is the condition setting signal 15.
Second, for example, if input information is received from a keyboard 1 (not shown), etc., and it is analyzed by Ifil, it indicates the store address value + data condition setting. First, address/data condition setting signal line 21
Initialize the setting register 11 (4) and then store the sequentially input address (direct) and data through the store address, data row ('l setting register group). Step up to 4] Go from 1 to 4.

In addition, by solving the human power information, the information of the 1 function key input from the keyboard L- etc. When 13 is a function key indicating the setting of fetch address planting data conditions, first, the phenotyal system data condition setting register group 10 is initialized via the address/data condition setting information 21. and the next sequentially input addresses (Direct and Data (
The operation controller 1-) is sequentially sent to the fetch address/data condition setting register 1ir10, and the row (
.

Here, the store that was created in this way
The contents of the data article ('l setting I/register group 4 and fetch address/data condition setting register group 10 are, for example,
The information is displayed on a display device (shown as -U).

In addition, after manually inputting such address data, a predetermined conditional logical formula, for example, Imperial Encyclopedia, AND,
Logic filter 2 is encoded by the combination of OR and NOT each time. is performed on each input address value data ILE, 4-, and the logical operation result is judgment data CI, C2.

As C3, .

Now, the information processing device 30 operates and selects the predetermined T row P1.
The durams are processed sequentially, and the register 1
In response to the store command, a predetermined address value is stored in the memory data register 2, and the take read at that time is stored in the memory data register 2.

Suppose that the At this time, the scope signal is generated on the store condition determination strobe signal line 3, and the store address/data condition determiner 5 is activated.

As a result, the store address/data condition setting register group 4 is compared with the data from each address skin grafted in memory 1-res register 1 and the data from normal data register 2. hand,
As a result, when there is a match 1) Rus j Q part Ai 4 Theta 1, a part Di (however, i is one of 1 to 11), the store address/data condition judger 5 sets the logical variable register Xi of the store/take condition logical variable register group 6 corresponding to the register (Ai → 1) i) in which a match has been found to Q (for example, logical value "0" or VJ, 1”).In addition,
In the case of a match for the stores 1i14j or in the case of no match, the logical variable register Xi is set to the initial state of false (for example, logical value "1" or "0")
It remains as it is.

Here, any address (if a match is found in the face data, the store address/data condition determiner 5
generates the strobe signal on the composite condition determination strobe signal line 13'' and sends it to the composite condition determination unit 18.

The complex condition determiner 18 receives this strobe signal, and
Logical variable register X1. X2. X3. ..., each part of Xn as a logical variable, is encoded according to a predetermined 8〆, ) logical formula, and the judgment data C
I, C2, C3,...

Interchange CL and these with J7. The agency's ancient fruits and talents 1.
lJ, III if a match is obtained with any signal from
An interrupt signal is generated on the Ji signal line 20''2, and the large t-1 of the 17th column is output at this point.

In response to this interruption signal, the processing device (1, 1) of the information processing device 30 enters a predetermined interruption process. Therefore, the operator checks the processing status of each part.

Here, logical variable registers XI, X2 . X3゜...
The tree of encoding each part of Set address/data conditions/Sister J! 1' If the address value is set to 4 and the number of takes is small, tl +,,l1
, 31, even if you compare it directly without encoding. In this case, the judgment data of the complex condition setter 16 is also the same, and matches the logical variable register corresponding to the number value or rank according to the corresponding input order.

Note that the judgment data CI, C2, C3 corresponding to the logical conditional expression
, . . . , CL, the number value that found a match (assuming that each '1' predetermined data has a predetermined number value corresponding to the subscript) is stored in the composite condition identification register 19. Get throated. Then, based on the contents of the complex condition identification register 19, for example, a corresponding number or directly which address value→-data for which a match was found is displayed on a display device (-U in the figure).

Next, one program of a predetermined execution program I' is sequentially processed, and a fetch instruction is stored in the operation register 7.
-Explain the case when

First, the faire address value is memory address register 1.
This data is sent to the store address/data condition determiner 5, the memory address register data line 8, and the fair address/operation condition determiner 11.
will be sent to. At the same time, a fetch command is set in the operation register 7 and sent to the phenocia 1-less operation condition determiner 11. Furthermore, the strobe signal is sent onto the fetch condition determination strobe signal line 1], and is supplied to the fetch address operation condition determiner 11.

As a result, the fetch address/operation one condition determiner 11 is activated, and the respective address values and data sent to the fetch address/data condition setting register group 10 are transferred to the address value from the memory address register 1 and the operation register. It is compared and verified with the data from 7.

Here, as in the case of the store, the address storage portion F A i-1 data record 1! :! Partial OP
The logical variable register Yi of the fetch address/data condition logical variable register group 12 corresponding to i (where i is one of 1 to m) is set to true. In addition,
In the case of a match of the phenothia l-less, the logical variable register Yi remains in its initial state f in the case of a non-match I,+2.

If any of the address values and data are the result of the verification,
When a match is found, in the same way as in the case of the above-mentioned swap (p, fetch address operation
1 multiplies the strophe signal on the compound condition judgment line LJ-B signal line]4 and sends the compound condition (') to the judge 18.

Complex row (71 determiner 18 &;I1, receives each strobe signal 14 -ζ, logical variable register Yl, Y2.Y3
゜..., Ym as logical variables af, 'i, encoded according to the above-mentioned predetermined logical formula, and sent out from the compound condition setter 16, the judgment data C1, C2
, C3,..., CI, and compare them.

As a result, if a match is obtained, an interruption signal iI+! 2
Generates an interrupt signal on J°0. This causes program execution to be interrupted at this point. Also, at this time,
Judgment data C1, C2, C3, etc. according to logical conditional expressions
. , C1, is set in the composite condition identification register 19.

In this way, the store address value data or the fetch address value data can be set as a set, and the 11J1 code in the execution program can be generated under conditions that match these sets. As a result, unless there is a plurality of programs in which these addresses and data match, it is possible to fold the target programs in the same state as the target program.

In addition, if there are cases where the address value - 1 data condition becomes 10,000 times in multiple programs, check the continuous match of the store address value → - data and phenosia 1 - data condition. By doing so, it can be determined that the desired processing state, etc. is present.

Furthermore, if multiple address conditions are set in advance so that multiple address values and data conditions for stores and fetches match consecutively, it is possible to achieve the desired result. It is possible to distinguish between interruptions in the program or unrelated interruptions. Therefore,
This means that the desired suspended state can be reached more quickly. In addition, for example, registers and A
N I) It is also possible to add a circuit or the like and adopt an AND condition of a match between the store address planting data and the edge address value → - data as the middle 11Ji condition.

Further, in the embodiment, a composite determination device is used to perform the determination after encoding, but a match may be detected by directly comparing the determination signal and the setting signal as described above.

Furthermore, it is of course possible to adopt either one of the store address value 10 data or Hue notialus planting data, and furthermore, these address values → - data are set to If address values and data are associated with each other, there is no need to store them in the form of a piece of paper.

By the way, the ten address conditions that should be set are:
Although this is done manually using a keyboard or the like, a function corresponding to the keyboard or the like may be provided in the compound condition setter.

Also, address conditions that should be set.

Although the gist data conditions are stored in a register, they may also be stored in a predetermined storage area of a memory by the information processing device, and the verification can be performed by arithmetic processing.

In short, the configuration of the present invention is such that a condition setting means for setting an address condition and a data condition is provided, and it is sufficient to satisfy the two conditions of the address condition and the data condition ('I). be.

〔Effect of the invention〕

As can be understood from the above description, the present invention provides an I+'7 information processing word processing device having a function of interrupting the processing of an execution program in accordance with a predetermined address condition ('l) set. Then, a condition setting means that can set a data condition together with an address condition is set up, and a program that does not claim that the two conditions (address condition and data condition) are established to cause the establishment to be opened. Or, in a predetermined processing state of the system, the processing can be easily and reliably interrupted.

As a result, confirmation of the processing operation of the executed program,
It is possible to realize an information processing device with a high reuse rate for tasks such as dehasing programs and investigating failures.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts of an information processing apparatus to which the present invention is applied. 1- Memoria 1-less register. 2- Memory data register. 3- Store condition determination strobe signal line. 4-S(・address/data condition setting register group,
5- Store address/data condition determiner, 6 =・-
Store data condition logic variable register group, 7-
Operation register. 8- Memory address register data line. 9- Fetch condition judgment strobe signal line. 10- Fetch address/operation control condition setting register group, l 1-----Fetch address/operation control R= Condition 41'l Regulator 12- Fencia 1-
゛Res operation condition logical variable register Il”r
. 13, 14--A compound condition determination strobe signal line. I5- Condition setting signal line, 16- Composite condition setter, 17
− Complex condition setting signal line. 18- 1 constant in compound condition, 19- compound column 1'l'
il's separate register, 20 - interrupted line. 2E - Atlus data condition setting signal line. 30- Information processing device patent applicant Fuji Electric Manufacturing Co., Ltd. Fuji Facom Control Co., Ltd. Agent Patent attorney Tetsuya Mori Patent attorney Nagoya Yoshiaki Patent attorney Masaru Shimizu Patent attorney Kaze Oriyama

Claims (3)

[Claims] (1) In an information processing device having a function of interrupting the processing of an execution program according to a predetermined address condition that has been set, a condition setting means for setting the address condition and a data condition ('l) is provided, and An information processing apparatus characterized in that the middle tlji is performed when two conditions, an address condition and a data condition, are met. (2) The condition setting means is configured to write the address value and the data corresponding thereto as the termination condition in 1. The address condition and the data condition are satisfied by comparing the address value accessed by the execution program and the data corresponding thereto with the address value and the data corresponding thereto serving as the interruption condition. The information processing apparatus according to claim 1, characterized in that the information processing apparatus is based on a collation means. (3) The address value that becomes the middle IJi condition and the corresponding U! - As an example, Phenocia I.Res (direct and has a plurality of first sets of data and a plurality of second sets of store address values and data, and the collator 1★ is the fetch address value of the execution program and this The data corresponding to the store address value and each of the plurality of first sets are collated, and the store address value and the data corresponding thereto are collated with each of the plurality of second sets. The information processing device according to item 2.