JPS606236U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS606236U
JPS606236U JP1983098167U JP9816783U JPS606236U JP S606236 U JPS606236 U JP S606236U JP 1983098167 U JP1983098167 U JP 1983098167U JP 9816783 U JP9816783 U JP 9816783U JP S606236 U JPS606236 U JP S606236U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
cap
glass
ceramic substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983098167U
Other languages
English (en)
Inventor
克朗 平岩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1983098167U priority Critical patent/JPS606236U/ja
Publication of JPS606236U publication Critical patent/JPS606236U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来の半導体装置の模式的構成図、第２図は本
考案の一実施例の模式的構成図である。 図において、２１はセラミック基板、２２゜２４はガラ
ス封止する接着面、２３はキャップ、２５．２６は凹凸
部を示す。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体チップを搭載するセラミック基板とキャップとの
    間に複数のリードを保持し、両者をガラスで接着して成
    り、少な（とも該セラミック基板と該キャップの一方の
    接着面に、凹凸部が設けられていることを特徴とする半
    導体装置。
JP1983098167U 1983-06-24 1983-06-24 半導体装置 Pending JPS606236U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983098167U JPS606236U (ja) 1983-06-24 1983-06-24 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983098167U JPS606236U (ja) 1983-06-24 1983-06-24 半導体装置

Publications (1)

Publication Number Publication Date
JPS606236U true JPS606236U (ja) 1985-01-17

Family

ID=30233193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983098167U Pending JPS606236U (ja) 1983-06-24 1983-06-24 半導体装置

Country Status (1)

Country Link
JP (1) JPS606236U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020136495A (ja) * 2019-02-20 2020-08-31 中央電子工業株式会社 中空パッケージ構造およびその製造方法、ならびに半導体装置およびその製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5111763B1 (ja) * 1971-06-30 1976-04-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5111763B1 (ja) * 1971-06-30 1976-04-14

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020136495A (ja) * 2019-02-20 2020-08-31 中央電子工業株式会社 中空パッケージ構造およびその製造方法、ならびに半導体装置およびその製造方法

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