JPS5844842U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5844842U
JPS5844842U JP1981139979U JP13997981U JPS5844842U JP S5844842 U JPS5844842 U JP S5844842U JP 1981139979 U JP1981139979 U JP 1981139979U JP 13997981 U JP13997981 U JP 13997981U JP S5844842 U JPS5844842 U JP S5844842U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
mount portion
abstract
lead frame
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981139979U
Other languages
English (en)
Inventor
嶋田　利泰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1981139979U priority Critical patent/JPS5844842U/ja
Publication of JPS5844842U publication Critical patent/JPS5844842U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/334—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図ａ、　　ｂはそれぞれ従来の半導体装置を示す部
分断面図、第２図は本考案の一実施例を示す部分断面図
である。 １・・・・・・リードフレーム、２・・・・・・ろう材
、３−−−−−−半導体チップ、４・・・・・・スルー
ホール。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体チップがリードフレームのマウント部にろう材を
    介して接着固定された半導体装置において、上記マウン
    ト部にスルーホールが形成されていることを特徴とする
    半導体装置。
JP1981139979U 1981-09-21 1981-09-21 半導体装置 Pending JPS5844842U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981139979U JPS5844842U (ja) 1981-09-21 1981-09-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981139979U JPS5844842U (ja) 1981-09-21 1981-09-21 半導体装置

Publications (1)

Publication Number Publication Date
JPS5844842U true JPS5844842U (ja) 1983-03-25

Family

ID=29933154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981139979U Pending JPS5844842U (ja) 1981-09-21 1981-09-21 半導体装置

Country Status (1)

Country Link
JP (1) JPS5844842U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413903U (ja) * 1987-07-17 1989-01-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413903U (ja) * 1987-07-17 1989-01-24

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