JPS6070820A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention relates to a semiconductor integrated circuit device.

Conventionally, an NTI (non-threshold logic) circuit as shown in FIG. 1 has been known.

Such an NTL circuit has a problem in that its operating level margin deteriorates depending on the type of load. For example, when the output has a wired logic configuration, the combined load resistance changes depending on the number of signal lines.
Alternatively, by connecting with relatively long wiring, wiring resistance is interposed between the logic chips 1 and 1, making the load non-uniform between them.

Therefore, the inventor of the present invention considered selectively using any NTl-circuit as a pseudo ECL (emitter coupled logic) circuit.

An object of the present invention is to provide a semiconductor integrated circuit device with a simple configuration and an expanded operating margin.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 2 shows a circuit diagram of an embodiment of a logic gate circuit used in a semiconductor integrated circuit device according to the present invention.

The parallel human-powered transistors Q1 to Q3 and the resistors R1 and R2 provided at their collectors and emitters, respectively, constitute an input stage circuit of the NTL circuit. The emitter follower output 1-transistor Q4 receiving the common collector output of the transistors Ql-Q3 constitutes the output stage circuit.

Since such an NTL circuit is well known, a detailed explanation of its operation will be omitted.

In this embodiment, a transistor Q5 is provided for each NTL circuit having the above configuration. Although not particularly limited, the collector of this transistor Q5 is connected to a positive power supply terminal (OV), and its emitter is connected to the common emitter of the human-powered transistors Q1 to Q3.

Then, the base is connected to the reference voltage VB [l side (a) or negative power terminal -V by a known master slicing method.
E" is selectively connected to the side (b).The above group Y
When r-voltage VRB is applied to the base of transistor Q5, transistors Q1 to Q3 and transistor Q5
Since they operate differentially, it operates as an ECL1 path that uses the reference voltage V as the logic threshold voltage. on the other hand,
When the above power supply voltage -VEE is applied to the base of transistor Q5, it operates as an NTLl path without a constant logic threshold voltage, and the junction capacitance I'J between transistors Q1 and Q5 is
It is provided between the common emitter of Q3 and the power supply terminal -VEE, and acts as a speed amplifier capacitor.

FIG. 3 shows a layout diagram of an embodiment of the above logic circuit according to the present invention.

The part surrounded by a broken line in the figure shows the basic cells G1 to G4 constituting the NTL circuit including the above-mentioned 1-transistor Q5.
is formed. Although not particularly limited, a first layer of aluminum wiring for supplying the reference voltage BB shown by a solid line runs horizontally in the center thereof. This wiring has a base tj4 area B that constitutes the transistor Q5.
The contact hole connected to
IfVBB is supplied. In this embodiment, when the holes 1 to 1 are not provided, the transistor Q
The base of No. 5 is left open.

Further, the method of selectively connecting the first layer aluminum wiring supplying the reference voltage V[]B and the base region B is not limited to the above embodiment. For example, the above-mentioned contact holes are formed in advance in all base areas B. Next, the first layer of aluminum wiring is formed by appropriately modifying its pattern. Thereby, the first Mth aluminum wire can be connected to the desired base region B via the holes 1 to 1. According to this method, the circuit configuration can be easily switched by simply changing the pattern of the first FJ aluminum wiring.

FIG. 4 shows a circuit diagram of a logic gate circuit according to an embodiment of the present invention.

In this embodiment, logic gate circuits E CL 1 to ECL
3, the circuit whose output has a wired logic configuration is operated as a substantial ECL circuit by applying a base voltage VBε to the base of Ranjisk Q5. . On the other hand, logic gate circuits NTL1 to NTL
TI, 3, whose output does not have a wired logic configuration.'' By applying a negative power supply voltage -VFE to the base of the transistor Q5 in the embodiment circuit of FIG.
Operate as a T+- circuit. In this way, in this embodiment, the connections are made so as to have an E C1 circuit or an NTL circuit configuration depending on the logical form.

In this embodiment, the logic gate block, which adopts a logic configuration in which the operation level margin as an NTL circuit is severe as described in 1-5, can secure the level margin by operating as an ECL1 circuit. On the other hand, N.T.L.
Even if a circuit is used, there is sufficient operating level margin (the logic game i-block that adopts the logic configuration is
It is designed to operate one by one as an L circuit. therefore,
Must be XJ3! It is possible to obtain a digital semiconductor integrated circuit that realizes high-speed operation while ensuring a reasonable operating margin.

Moreover, the above-mentioned l-transistor Q5 can be applied with a negative power supply voltage -VEF as in the embodiment circuit of FIG. 2, or in an open state as in the embodiment of FIG. 3, depending on its junction capacitance. Since it acts as a speed reducing capacitor for the NTL circuit, it can be used effectively.

Furthermore, if the circuit configuration is determined by the master slicing method as described above, there is no need to increase the number of manufacturing steps.

The invention is not limited to the above implementation sequence.

The transistor Q5 may have its collector and emitter/7 terminal connections switched according to its logical configuration.・The emitter of transistor Q5 is fixedly connected in the same manner as above, and its base is selectively connected to the emitter side.
The wiring means for switching the base wiring of the transistor Q5 uses the 21Nth aluminum layer. Various embodiments may be adopted.

The present invention can be widely applied to semiconductor integrated circuit devices that perform various types of information processing.

[Brief explanation of the drawing]

Figure 1 is a 1/3 diagram of a conventional NTI circuit without showing an example of the circuit. Figure 2 is a circuit diagram of a logic gate circuit showing an example of the present invention. Figure 3 is a diagram of its layout. -(RI1. I tZ layout diagram, Figure 4 is a circuit diagram of one row of one embodiment of this invention. Figure 1 Figure 2 Figure 3 Figure 4 Figure C/T and 2

Claims (1)

[Claims] 1. NTL with emitter follower output transistor
1. A semiconductor integrated circuit device comprising a gate L-circuit and a transistor selectively connected in a differential manner to an input stage transistor of the NTL gate circuit and having a reference voltage applied to its gate. 2. The transistors that are selectively made into a differential type are used in correspondence with each NTL gate circuit, and are selectively made into the differential type with respect to the human-powered 19+/Run transistors using the Mano-Kuslais method. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is connected in a differential configuration or as a speed-up capacitor.