JPS597247B2 - semiconductor logic circuit - Google Patents

semiconductor logic circuit

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Publication number
JPS597247B2
JPS597247B2 JP47044072A JP4407272A JPS597247B2 JP S597247 B2 JPS597247 B2 JP S597247B2 JP 47044072 A JP47044072 A JP 47044072A JP 4407272 A JP4407272 A JP 4407272A JP S597247 B2 JPS597247 B2 JP S597247B2
Authority
JP
Japan
Prior art keywords
logic
control terminal
logic circuit
chip
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP47044072A
Other languages
Japanese (ja)
Other versions
JPS495258A (en
Inventor
弘道 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP47044072A priority Critical patent/JPS597247B2/en
Publication of JPS495258A publication Critical patent/JPS495258A/ja
Publication of JPS597247B2 publication Critical patent/JPS597247B2/en
Expired legal-status Critical Current

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  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は集積化された半導体論理回路に関し、特にその
入力又は出力或はその両者と論理振巾がことなった論理
信号との受け渡しを簡単に可能にしたものに係わる。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated semiconductor logic circuit, and in particular to one that allows easy exchange of logic signals with different logic amplitudes between its inputs, outputs, or both. .

近時集積化技術の進歩に伴って大規模稠密構造の集積回
路(以下LSIと記す)が一般化しつつある。
2. Description of the Related Art With recent advances in integration technology, large-scale dense integrated circuits (hereinafter referred to as LSIs) are becoming more common.

LSIでは多数個の論理回路を同時に一つの半導体基板
(以下チップと記す)に形成するため、チップ内ゲート
は外部雑音の影響を受け難く、従ってLSIの高速化を
はかるため雑音マージンの小さな小論理振巾の論理回路
が使われる傾向にある。
In LSI, many logic circuits are formed simultaneously on one semiconductor substrate (hereinafter referred to as a chip), so the gates within the chip are less susceptible to external noise. Therefore, in order to increase the speed of LSI, small logic circuits with a small noise margin are There is a tendency for a wide range of logic circuits to be used.

しかしLSIチップ間の信号接続はチップ内信号配線長
に比べ1〜2桁も長くなるので外部雑音の影響を無視で
きない。
However, since the signal connections between LSI chips are one to two orders of magnitude longer than the length of the signal wiring within the chip, the influence of external noise cannot be ignored.

よってLSIチップのごく近傍でチップ論理回路の出力
レベルを変換して論理振巾を大きくし雑音に強い論理信
号として外部へ供給し、また逆に大きな論理振巾の信号
を小さい論理振巾の信号に変換してLSIチップの論理
回路へ供給する方法が採られている。
Therefore, the output level of the chip logic circuit is converted in the vicinity of the LSI chip to increase the logic amplitude and is supplied to the outside as a noise-resistant logic signal, and conversely, a signal with a large logic amplitude can be converted into a signal with a small logic amplitude. A method has been adopted in which the signal is converted into a signal and then supplied to the logic circuit of the LSI chip.

しかしこの方法では、LSIチップ以外にレベル変換用
のチップが必要であり、装置構成時に、実装上の煩雑さ
が増し、コスト上昇をきたし、実装密度が低下するなど
の欠点があった。
However, this method requires a level conversion chip in addition to the LSI chip, which increases the complexity of mounting when configuring the device, increases cost, and reduces packaging density.

この発明の目的は論理回路が形成された半導体集積回路
自体において必要に応じて大きな論理振巾の信号を受け
ることができ、或は論理振巾の大きい外部論理回路へ出
力を供給できる変換機能を有する半導体論理回路を提供
するにある。
The purpose of this invention is to provide a conversion function that can receive a signal with a large logic width as needed in the semiconductor integrated circuit itself in which a logic circuit is formed, or supply an output to an external logic circuit with a large logic width. An object of the present invention is to provide a semiconductor logic circuit having a semiconductor logic circuit.

本発明によればLSIチップに前もって準備された制御
端子に制御信号を与えることにより、出力端子には大き
くなった論理振巾を出力し、入力端子には大きな論理振
巾を受け入れることができるようになされる。
According to the present invention, by applying a control signal to a control terminal prepared in advance on an LSI chip, it is possible to output a larger logic width to the output terminal and accept a larger logic width to the input terminal. done to.

このため例えば定電流源を使用した電流切換型論理回路
LSIチップにおいて、チップ外へ接続された出力端子
を有する出力部論理回路には2つの定電流源を準備し、
その1つは制御端子を設け、一方の定電流源は常時動作
するも、他方の定電流源は上記制御端子に規定の定電圧
(制御信号)が加えられたとき、始めて動作する。
For this reason, for example, in a current switching type logic circuit LSI chip using constant current sources, two constant current sources are prepared in the output logic circuit having an output terminal connected to the outside of the chip.
One of them is provided with a control terminal, and while one constant current source operates at all times, the other constant current source only operates when a specified constant voltage (control signal) is applied to the control terminal.

このようにして出力部論理回路の負荷抵抗に流れる電流
が二つの値の一方をとることができ、電流を大きくする
時は、論理レベルが犬となる。
In this way, the current flowing through the load resistance of the output logic circuit can take one of two values, and when the current is increased, the logic level becomes a dog.

一方チップ外へ接続された入力端子を有する入力部論理
回路に同様に2つの定電流源を有し、その1つは常時動
作するも、他方は制御端子に制御信号が与えられた時の
み動作し、制御端子に制御信号を供給するか否かにより
基準電圧が得られる抵抗素子に流れる電流が二つの値に
切替えられる。
On the other hand, the input logic circuit that has an input terminal connected to the outside of the chip similarly has two constant current sources, one of which operates all the time, while the other operates only when a control signal is applied to the control terminal. However, depending on whether or not a control signal is supplied to the control terminal, the current flowing through the resistance element from which the reference voltage is obtained is switched between two values.

これに大電流を流した時、入力部論理回路の基準電圧が
大とされる。
When a large current is passed through this, the reference voltage of the input logic circuit becomes large.

必要に応じて出力部論理回路及び入力部論理回路のそれ
ぞれの上記制御端子をチップ内で接続してチップ外へ共
通制御端子として取り出すことができる。
If necessary, the control terminals of the output logic circuit and the input logic circuit can be connected within the chip and taken out as a common control terminal outside the chip.

次に図面を参照して本発明を詳細に説明しよう。The invention will now be explained in detail with reference to the drawings.

第1図は定電流源を使用した電流切換型論理回路の一具
体例を示す図で電流切換回路用トランジスタQl,Q2
,Q3及び論理レベルを発生する負荷抵抗R1R2及び
定電流源Q4 ,R3から成り、入力端子1,2、出
力端子3,4、基準電圧端子5、定電流源基準電圧端子
6を有する。
Figure 1 is a diagram showing a specific example of a current switching type logic circuit using a constant current source.
, Q3, a load resistor R1R2 that generates a logic level, and constant current sources Q4, R3, and has input terminals 1 and 2, output terminals 3 and 4, a reference voltage terminal 5, and a constant current source reference voltage terminal 6.

第1図の論理回路を動作させるには定電流源基準電圧端
子6に適当な定電圧を与え、定電流回路を動作させ、基
準電圧端子5に論理レベル゛1”及び”0”の中間の基
準電圧を与え、入力端子1,2に論理信号電圧を加える
ことによって、出力端子3には逆相の論理出力を、出力
端子4には同相の論理出力をそれぞれ得る。
To operate the logic circuit shown in FIG. 1, apply an appropriate constant voltage to the constant current source reference voltage terminal 6, operate the constant current circuit, and set the reference voltage terminal 5 to a level between logic levels "1" and "0". By applying a reference voltage and applying logic signal voltages to input terminals 1 and 2, an opposite-phase logic output is obtained at output terminal 3, and an in-phase logic output is obtained at output terminal 4.

出力端子3又は4に現われる出力レベル(すなわち論理
振巾)は定電流電源Q4tR3と抵抗R1,R2の抵抗
値とによって決まることは明らかである。
It is clear that the output level (ie, logic amplitude) appearing at the output terminal 3 or 4 is determined by the constant current power supply Q4tR3 and the resistance values of the resistors R1 and R2.

第2図は第1図の基準電圧端子5に加える基準電圧を発
生する基準電圧回路の一具体例を示す回路であり、第1
図と同じ回路構成の定電流源QstR5と基準電圧が得
られる抵抗R4 とからなっている。
FIG. 2 is a circuit showing a specific example of a reference voltage circuit that generates a reference voltage to be applied to the reference voltage terminal 5 of FIG.
It consists of a constant current source QstR5 having the same circuit configuration as shown in the figure and a resistor R4 from which a reference voltage is obtained.

基準電圧は論理レベル゛1”及び“0”の中間に設定さ
れるから、定電流源の電流を第1図のそれと同じとすれ
ば抵抗R4の抵抗値を抵抗R1又はR2の抵抗値の半分
に選ぶことにより希望する基準電圧を容易に得ることが
できる。
Since the reference voltage is set between logic levels "1" and "0", if the current of the constant current source is the same as that in Figure 1, the resistance value of resistor R4 is half the resistance value of resistor R1 or R2. By selecting , the desired reference voltage can be easily obtained.

?3図は本発明による半導体論理回路の1具体例を示し
、LSIチップ内の論理回路を模形的に説明した図であ
り、外側実線のわくはLSIチップの境界を示している
? FIG. 3 shows a specific example of a semiconductor logic circuit according to the present invention, and is a diagram schematically explaining a logic circuit within an LSI chip, and the outer solid line frame indicates the boundary of the LSI chip.

LSIチップ内の論理回路は、入力がチップ外に接続さ
れている入力部論理回路A、入出力共チップ内論理回路
と接続され、チップ外へは出ないものB、出力がチップ
外へ接続されるものCの3つに分けることができる。
The logic circuits inside the LSI chip are input part logic circuit A whose input is connected to the outside of the chip, input part logic circuit A which has both input and output connected to the logic circuit inside the chip and does not go outside the chip, and logic circuit B whose output is connected to the outside of the chip. It can be divided into three types: C.

第3図で論理回路A,Cに共通に接続された点線は定電
流源の制御線を示している。
In FIG. 3, the dotted line commonly connected to the logic circuits A and C indicates the control line of the constant current source.

第4図は第3図論理回路Aに本発明を適用した回路構成
の一実施例を示す図で、基準電圧回路は2つの同じ特性
の定電流源Q1o,R10 ,Q11,R1を有し、1
つの定電流源Q11,R11は制御端子12が導出され
、他の1つの定電流源QIO tR10はチップ内の定
電流源基準電圧を与える定電圧に接続される端子11を
有する。
FIG. 4 is a diagram showing an example of a circuit configuration in which the present invention is applied to the logic circuit A in FIG. 1
Control terminals 12 are led out from the two constant current sources Q11 and R11, and the other constant current source QIO tR10 has a terminal 11 connected to a constant voltage that provides a constant current source reference voltage within the chip.

制御端子12に定電圧(制御信号)が加えられなければ
トランジスタQ1は遮断状態にあるから、第4図の回路
は第1図の論理回路と同じ動作をする。
If a constant voltage (control signal) is not applied to the control terminal 12, the transistor Q1 is in a cutoff state, so the circuit of FIG. 4 operates in the same way as the logic circuit of FIG. 1.

即ちトランジスタQ3のベースに接続される基準電圧は
第1図の論理回路の論理振巾の中央に設定され、小さい
論理振巾に対する基準を与える。
That is, the reference voltage connected to the base of transistor Q3 is set at the center of the logic amplitude of the logic circuit of FIG. 1, providing a reference for small logic amplitudes.

入力端子9又は10に加えられる論理入力電圧が大きく
なった(例えば第4図のトランジスタQ6 ,Q7 ,
Q8のコレクタでの論理振巾の2倍)とすれば論理回路
の基準電圧(トランジスタQ8のベース電位)は論理″
1”側にずれることになる。
The logic input voltage applied to input terminal 9 or 10 is increased (e.g. transistors Q6, Q7, Q7 in FIG.
(twice the logic width at the collector of Q8), the reference voltage of the logic circuit (base potential of transistor Q8) is logic
It will shift to the 1" side.

即ち論理振巾の1/4の所に基準電圧が位置することに
なり、正しい基準電圧として動作しなくなり、誤動作す
るおそれが生じる。
In other words, the reference voltage will be located at 1/4 of the logic amplitude, and will no longer operate as a correct reference voltage, resulting in a risk of malfunction.

しかし制御端子12を定電流源基準電圧端子11に接続
するとトランジスタQllも導通し、基準電圧を発生す
る抵抗R8には今迄の2倍の電流が流れるので基準電圧
は2倍となり、入力に加えられた2倍の論理振巾の中央
に基準電圧が設定され、この論理回路は正しく動作する
However, when the control terminal 12 is connected to the constant current source reference voltage terminal 11, the transistor Qll also becomes conductive, and twice as much current flows through the resistor R8 that generates the reference voltage. The reference voltage is set at the center of the double logic width, and this logic circuit operates correctly.

即ち入力論理信号のレベルが大きい場合に正しい動作が
可能となる。
That is, correct operation is possible when the level of the input logic signal is high.

例では2倍の入力論理振巾で考えたが、入力論理振中ば
2倍である必要がなく入力論理振巾に応じた基準電圧を
発生させるには、抵抗R1の値を変えることで任意の基
準電圧を発生できることは明らかである。
In the example, we considered the input logic width to be twice, but it is not necessary to double the input logic width, and in order to generate a reference voltage according to the input logic width, you can change the value of the resistor R1. It is clear that it is possible to generate a reference voltage of .

また抵抗Rllの値を変えたくない場合は制御端子12
に加える定電圧を変えても同様な効果を得ることができ
る。
Also, if you do not want to change the value of the resistor Rll, use the control terminal 12.
A similar effect can be obtained by changing the constant voltage applied to.

即ち第4図の回路は制御端子12を制御することにより
論理振巾の変換(レベル変換)が可能となることがわか
る。
That is, it can be seen that the circuit shown in FIG. 4 allows logic amplitude conversion (level conversion) by controlling the control terminal 12.

第5図は第3図の出力部論理回路Cに本発明を適用した
ー実施例を示す図である。
FIG. 5 is a diagram showing an embodiment in which the present invention is applied to the output section logic circuit C of FIG. 3.

この図では電流切換回路部に2つの定電流源Q15 t
R15 t Qta tR16を持つ構成となってい
る。
In this figure, there are two constant current sources Q15 t in the current switching circuit section.
The configuration has R15 t Qta tR16.

1つの定電流源Q159R15には制御端子17を有し
、他の定電流源Q16,R16の定電流源基準電圧端子
18はチップ内の定電圧が与えられるものである。
One constant current source Q159R15 has a control terminal 17, and the constant current source reference voltage terminals 18 of the other constant current sources Q16 and R16 are supplied with a constant voltage within the chip.

制御端子17に定電圧(制御信号)が加えられていない
ときは、第5図の論理回路は第1図の論理回路に等しい
論理レベルで動作するが、制御端子1γを端子18に接
続しかつ抵抗R 15の抵抗値を抵抗R16の抵抗値に
等しく取れば電流切換回路部には前の状態に比較して2
倍の電流が流れ、従って出力端子15又は16に現われ
る論理振巾も2倍となる。
When no constant voltage (control signal) is applied to control terminal 17, the logic circuit of FIG. 5 operates at the same logic level as the logic circuit of FIG. If the resistance value of resistor R15 is made equal to the resistance value of resistor R16, the current switching circuit section will have 2
Double the current flows and therefore the logic amplitude appearing at the output terminal 15 or 16 also doubles.

この説明ではトランジスタQ15抵抗R15より成る定
電流回路を、トランジスタQ16抵抗R16より成.る
定電流源と同じ特性として考えたが、必ずしもこの必要
はなく、出力端子15又は16に現わす論理振巾な任意
に変えることができるのは第4図につき説明した場合と
同じである。
In this explanation, a constant current circuit made up of a transistor Q15 and a resistor R15 is made up of a transistor Q16 and a resistor R16. Although the characteristic is considered to be the same as that of a constant current source, this is not necessarily necessary, and the logic width appearing at the output terminal 15 or 16 can be arbitrarily changed as in the case explained with reference to FIG.

即ち第5図に於ては制御端子17に制御信号を与えたり
、外したりすることにより出力端子15.16の出力論
理振巾を大きくしたり小さくしたりできる。
That is, in FIG. 5, by applying or removing a control signal to the control terminal 17, the output logic amplitude of the output terminals 15 and 16 can be increased or decreased.

上述した本発明による半導体論理回路によれば基準電圧
が得られる抵抗R8、又は負荷抵抗R12,R12に流
れる電流を、定電流源の制御端子に対する電圧制御信号
で動作、不動作制御して、このチップに接続される外部
の論理回路の論理振巾に合せて基準電圧を大きくしたり
、論理レベルを大きくしたりすることができる。
According to the semiconductor logic circuit according to the present invention described above, the current flowing through the resistor R8 from which the reference voltage is obtained or the load resistors R12, R12 is controlled to be activated or deactivated by the voltage control signal to the control terminal of the constant current source. It is possible to increase the reference voltage or increase the logic level in accordance with the logic amplitude of an external logic circuit connected to the chip.

従ってLSIチップ内では論理回路を低電力で高速動作
させることができ、非常に小さい論理振巾とし余分なレ
ベル変換用チップを使用せずに、チップ外へは論理振巾
を大きくして動作させることができる。
Therefore, logic circuits can operate at low power and high speed inside the LSI chip, with very small logic widths and without using extra level conversion chips, and outside the chip, logic circuits can be operated with large logic widths. be able to.

よって実装密度は高まり、余分なレベル変換チップも使
用しないので、コストを下げることも可能である。
Therefore, packaging density is increased, and since no extra level conversion chip is used, it is also possible to reduce costs.

更に本発明によるLSIチップを製造することにより例
えばマルチチップLSI(多数個のチップを例えば相互
配線されたアルミナ基板上に実装してLSIを構成する
もの)のようにアルミナ基板内では小論理振巾動作し、
アルミナ基板から外側では大論理振巾動作としたいとき
にも、アルミナ基板の端子に接続されているチップは制
御端子と定電流源基準定電圧端子を短絡することにより
容易に目的を達成することができるので異なった論理振
巾のLSIチップを製造する必要がなく、その経済的効
果は大きい。
Furthermore, by manufacturing an LSI chip according to the present invention, a small logic width can be achieved within an alumina substrate, such as a multi-chip LSI (an LSI configured by mounting a large number of chips on an alumina substrate interconnected with each other). Work,
Even when it is desired to operate with a large logic width outside the alumina substrate, the purpose can be easily achieved by short-circuiting the control terminal of the chip connected to the terminal of the alumina substrate and the constant current source reference constant voltage terminal. Therefore, there is no need to manufacture LSI chips with different logic widths, which has a large economic effect.

上述においては主としてNPN}ランジスタを用いたL
SIチップにより本発明の動作を説明したがPNP }
ランジスタを用いたLSIチップにも本発明は適用でき
る.またLSIチップの入力部論理回路、出力部論理回
路の一方にのみ本発明を適用することもできる。
In the above description, L mainly uses NPN} transistors.
Although the operation of the present invention was explained using an SI chip, PNP }
The present invention can also be applied to LSI chips using transistors. Further, the present invention can also be applied to only one of the input logic circuit and the output logic circuit of an LSI chip.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は定電流源を使用した従来の電流切換回路を示す
接続図、第2図は基準電圧を発生する回路図、第3図は
本発明による半導体論理回路を使用したLSIチップの
論理構成を示すブロック図、第4図は本発明による半導
体論理回路の入力部論理回路の一実施例を示す接続図、
第5図は本発明による半導体論理回路の出力部論理回路
の一実施例を示す接続図である。 A・・・入力部論理回路、C・・・出力部論理回路。
Fig. 1 is a connection diagram showing a conventional current switching circuit using a constant current source, Fig. 2 is a circuit diagram for generating a reference voltage, and Fig. 3 is a logic configuration of an LSI chip using a semiconductor logic circuit according to the present invention. FIG. 4 is a connection diagram showing an embodiment of the input section logic circuit of the semiconductor logic circuit according to the present invention.
FIG. 5 is a connection diagram showing an embodiment of the output section logic circuit of the semiconductor logic circuit according to the present invention. A... Input section logic circuit, C... Output section logic circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 基準電圧に基いて論理動作を行ない、電流源に流れ
る電流を切換える電流切換型論理回路を入力部論理回路
および出力部論理回路として単一の集積回路チップ上に
それぞれ少なくとも1個備えた半導体集積回路において
、上記チップに設けられた外部制御端子と、上記外部制
御端子に接続され、該外部制御端子が第1のレベルの時
に第1の値の電圧を出力し、該外部制御端子が第2のレ
ベルの時に該第1の値よりも絶対値の大きい第2の値の
電圧を出力する基準電圧発生回路と、該基準電圧発生回
路の出力電圧を前記入力部論理回路に基準電圧として印
加する手段と、上記出力部論理回路における上記電流源
に並列に接続され、上記外部制御端子が上記第1のレベ
ルの時には機能せず、上記外部制御端子が上記第2のレ
ベルの時に所定の電流を出力する付加定電流源とを有し
、上記外部制御端子のレベルを制御することにより、前
記チップ外の異なる論理振幅の信号に対して上記チップ
を接続しつるようにしたことを特徴とする半導体集積回
路。
1. A semiconductor integrated circuit comprising at least one current switching type logic circuit that performs a logic operation based on a reference voltage and switches the current flowing through a current source as an input logic circuit and an output logic circuit on a single integrated circuit chip. In the circuit, an external control terminal provided on the chip is connected to the external control terminal, the external control terminal outputs a voltage of a first value when the external control terminal is at a first level, and the external control terminal outputs a voltage of a first value when the external control terminal is at a first level. a reference voltage generation circuit that outputs a voltage of a second value whose absolute value is larger than the first value when the level is , and the output voltage of the reference voltage generation circuit is applied as a reference voltage to the input logic circuit. and means connected in parallel to the current source in the output logic circuit, which do not function when the external control terminal is at the first level and supply a predetermined current when the external control terminal is at the second level. and an additional constant current source that outputs an additional constant current source, and by controlling the level of the external control terminal, the chip can be connected to signals of different logic amplitudes outside the chip. integrated circuit.
JP47044072A 1972-05-01 1972-05-01 semiconductor logic circuit Expired JPS597247B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP47044072A JPS597247B2 (en) 1972-05-01 1972-05-01 semiconductor logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP47044072A JPS597247B2 (en) 1972-05-01 1972-05-01 semiconductor logic circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP57004369A Division JPS57136820A (en) 1982-01-14 1982-01-14 Semiconductor logical circuit

Publications (2)

Publication Number Publication Date
JPS495258A JPS495258A (en) 1974-01-17
JPS597247B2 true JPS597247B2 (en) 1984-02-17

Family

ID=12681411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP47044072A Expired JPS597247B2 (en) 1972-05-01 1972-05-01 semiconductor logic circuit

Country Status (1)

Country Link
JP (1) JPS597247B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6249607U (en) * 1985-09-13 1987-03-27

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5546681A (en) * 1978-09-29 1980-04-01 Nec Corp Current switching type logic circuit
DE2903659A1 (en) * 1979-01-31 1980-08-14 Siemens Ag MONOLITHICALLY INTEGRATED LOGIC CIRCUIT
JPS566535A (en) * 1979-06-28 1981-01-23 Nec Corp Integrated circuit
JPS56160139A (en) * 1980-05-14 1981-12-09 Toshiba Corp I2l logical circuit
FR2491276A1 (en) * 1980-09-26 1982-04-02 Trt Telecom Radio Electr INTERFACE CIRCUITS BETWEEN LOGIC INJECTION LAYERS STACKED AND POLARIZED AT DIFFERENT VOLTAGES
GB2104747B (en) * 1981-08-25 1984-12-12 Standard Telephones Cables Ltd Integrated circuit power supplies
JPS5853228A (en) * 1981-09-25 1983-03-29 Nec Corp Semiconductor integrated circuit device
JPS59153330A (en) * 1983-02-21 1984-09-01 Hitachi Ltd Logical lsi
JPS6070820A (en) * 1983-09-28 1985-04-22 Hitachi Ltd Semiconductor integrated circuit device
JPH0750374B2 (en) * 1986-03-03 1995-05-31 凸版印刷株式会社 Original image capture method for flat holographic stereogram
JPS63138384A (en) * 1986-11-29 1988-06-10 Toppan Printing Co Ltd Manufacture of original picture of plane type holographic stereogram

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6249607U (en) * 1985-09-13 1987-03-27

Also Published As

Publication number Publication date
JPS495258A (en) 1974-01-17

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