JPS6126252B2 - - Google Patents

Info

Publication number
JPS6126252B2
JPS6126252B2 JP57004369A JP436982A JPS6126252B2 JP S6126252 B2 JPS6126252 B2 JP S6126252B2 JP 57004369 A JP57004369 A JP 57004369A JP 436982 A JP436982 A JP 436982A JP S6126252 B2 JPS6126252 B2 JP S6126252B2
Authority
JP
Japan
Prior art keywords
logic
constant current
logic circuit
reference voltage
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57004369A
Other languages
Japanese (ja)
Other versions
JPS57136820A (en
Inventor
Hiromichi Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57004369A priority Critical patent/JPS57136820A/en
Publication of JPS57136820A publication Critical patent/JPS57136820A/en
Publication of JPS6126252B2 publication Critical patent/JPS6126252B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/018Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806Interface arrangements
    • H03K19/01812Interface arrangements with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Description

【発明の詳細な説明】 本発明は集積化された半導体論理回路に関し、
特にその入力又は出力或はその両者と論理振幅が
ことなつて論理信号との受け渡しを簡単に可能に
したものに係る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated semiconductor logic circuit,
In particular, it relates to those whose inputs and/or outputs have different logic amplitudes, allowing easy exchange of logic signals.

近時集積化技術の進歩に伴つて大規模稠密構造
の集積回路(以下LSIと記す)が一搬化しつつあ
る。LSIでは多数個の論理回路を同時に一つの半
導体基板(以下チツプと記す)に形成するため、
チツプ内ゲートは外部雑音の影響を受け難く、従
つてLSIの高速化をはかるため雑音マージンの小
さな小論理振幅の論理回路が使われる傾向にあ
る。しかしLSIチツプ間の信号接続はチツプ内信
号配線長に比べ1〜2桁も長くなるので外部雑音
の影響を無視できない。よつてLSIチツプのごく
近傍でチツプ論理回路の出力レベルを変換して論
理振幅を大きくし雑音に強い論理信号として外部
へ供給し、また逆に大きな論理振幅の信号を小さ
い論理振幅の信号に変換してLSIチツプの論理回
路へ供給する方法が採られている。しかしこの方
法では、LSIチツプ以外にレベル変換用のチツプ
が必要であり、装置構成時に、実装上の煩雑さが
増し、コスト上昇をきたし、実装密度が低下する
などの欠点があつた。
With recent advances in integration technology, large-scale, densely structured integrated circuits (hereinafter referred to as LSI) are becoming increasingly common. In LSI, many logic circuits are formed simultaneously on one semiconductor substrate (hereinafter referred to as a chip).
In-chip gates are not easily affected by external noise, and therefore, in order to increase the speed of LSIs, there is a tendency to use logic circuits with small logic amplitudes and small noise margins. However, since the signal connections between LSI chips are 1 to 2 orders of magnitude longer than the signal wiring length within the chip, the influence of external noise cannot be ignored. Therefore, the output level of the chip logic circuit is converted in the vicinity of the LSI chip to increase the logic amplitude and supplied to the outside as a noise-resistant logic signal, and conversely, a signal with a large logic amplitude is converted to a signal with a small logic amplitude. A method is adopted in which the signal is then supplied to the logic circuit of the LSI chip. However, this method requires a level conversion chip in addition to the LSI chip, which increases the complexity of mounting when configuring the device, increases costs, and reduces packaging density.

この発明の目的は論理回路が形成された半導体
集積回路自体において必要に応じて大きな論理振
幅の信号を受けることができ、或は論理振幅の大
きい外部論理回路へ出力を供給できる変換機能を
有する半導体論理回路を提供するにある。
An object of the present invention is to provide a semiconductor integrated circuit in which a logic circuit is formed, which has a conversion function that can receive a signal with a large logic amplitude as needed, or supply an output to an external logic circuit with a large logic amplitude. To provide logic circuits.

本発明によればLSIチツプに前もつて準備され
た制御端子に制御信号を与えることにより、出力
端子には大きくなつた論理振幅を出力し、入力端
子には大きな論理振幅を受け入れることができる
ようになされる。このため定電流源を使用した電
流切換型論理回路LSIチツプにおいて、チツプ外
へ接続された出力端子を有する出力部論理回路に
は2つの定電流源を準備し、その1つは制御端子
を設け、一方の定電流源は常時動作するも、他方
の定電流源は上記制御端子に規定の定電圧(制御
信号)が加えられたとき、始めて動作する。この
ようにして出溶部論理回路の負荷抵抗に流れる電
流が二つの値の一方をとることができ、電流を大
きくする時は、論理レベルが大となる。
According to the present invention, by applying a control signal to a control terminal prepared in advance on an LSI chip, a larger logic amplitude can be output to the output terminal, and a larger logic amplitude can be accepted to the input terminal. done to. For this reason, in a current-switching logic circuit LSI chip that uses constant current sources, two constant current sources are prepared in the output logic circuit that has an output terminal connected to the outside of the chip, and one of them is provided with a control terminal. Although one constant current source operates all the time, the other constant current source only operates when a specified constant voltage (control signal) is applied to the control terminal. In this way, the current flowing through the load resistor of the effluent logic circuit can take one of two values, and when the current is increased, the logic level is increased.

次に図面を参照して本発明を詳細に説明しよ
う。
The invention will now be described in detail with reference to the drawings.

第1図は定電流源を使用した電流切換型論理回
路の一具体例を示す図で電流切換回路用トランジ
スタQ1,Q2,Q3及び論理レベルを発生する負荷
抵抗R1,R2及び定電流源Q4,Qから成り、入力
端子1,2、出力端子3,4、基準電圧端子5、
定電流源基準電圧端子6を有する。第1図の論理
回路を動作させるには定電流源基準電圧端子6に
適当な定電圧を与え、定電流回路を動作させ、基
準電圧端子5に論理レベル“1”及び“0”の中
間の基準電圧を与え、入力端子1,2に論理信号
電圧を加えることによつて、出力端子3には逆相
の論理出力を、出力端子4には同相の論理出力を
それぞれ得る。出力端子3又は4に現われる出力
レベル(すなわち論理振幅)は定電流電源Q4
R3と抵抗R1,R2の抵抗値とによつて決まること
は明らかである。
Figure 1 is a diagram showing a specific example of a current switching type logic circuit using a constant current source, which includes current switching circuit transistors Q 1 , Q 2 , Q 3 and load resistors R 1 , R 2 and Consisting of constant current sources Q 4 and Q, input terminals 1 and 2, output terminals 3 and 4, reference voltage terminal 5,
It has a constant current source reference voltage terminal 6. To operate the logic circuit shown in FIG. 1, apply an appropriate constant voltage to the constant current source reference voltage terminal 6, operate the constant current circuit, and apply a voltage between the logic levels "1" and "0" to the reference voltage terminal 5. By applying a reference voltage and applying logic signal voltages to input terminals 1 and 2, an opposite-phase logic output is obtained at output terminal 3, and an in-phase logic output is obtained at output terminal 4. The output level (i.e. logical amplitude) appearing at output terminal 3 or 4 is determined by constant current power supply Q 4 ,
It is clear that it is determined by R 3 and the resistance values of resistors R 1 and R 2 .

第2図は第1図の基準電圧端子5に加える基準
電圧を発生する基準電圧回路の一具体例を示す回
路であり、第1図と同じ回路構成の定電流源
Q5,R5と基準電圧が得られる抵抗R4とからなつ
ている。基準電圧は論理レベル“1”及び“0”
の中間に設定されるから、定電流源の電両を第1
図のそれと同じとすれば抵抗R4の抵抗値を抵抗
R1又はR2の抵抗値の半分に選ぶことにより希望
する基準電圧を容易に得ることができる。
Figure 2 shows a specific example of a reference voltage circuit that generates a reference voltage to be applied to the reference voltage terminal 5 in Figure 1, and is a constant current source with the same circuit configuration as in Figure 1.
It consists of Q 5 , R 5 and a resistor R 4 from which a reference voltage can be obtained. Reference voltage is logic level “1” and “0”
Since the voltage of the constant current source is set in the middle of
If it is the same as that in the figure, the resistance value of resistor R 4 is the resistance
A desired reference voltage can be easily obtained by selecting half the resistance value of R1 or R2 .

第3図は本発明を適用した半導体論理回路の1
具体例を示し、LSIチツプ内の論理回路を模形的
に説明した図であり、外側実線のわくはLSIチツ
プの境界を示している。LSIチツプ内の論理回路
は、入力がチツプ外に接続されている入力部論理
回路A、入出力共チツプ内論理回路と接続され、
チツプ外へは出ないものB、出力がチツプ外へ接
続されるものCの3つの分けることができる。第
3図で論理回路A,Cに共通に接続された点線は
定電流源の制御線を示している。
Figure 3 shows one of the semiconductor logic circuits to which the present invention is applied.
It is a diagram showing a specific example and schematically explaining a logic circuit within an LSI chip, and the outer solid line frame indicates the boundary of the LSI chip. The logic circuit inside the LSI chip has an input section logic circuit A whose input is connected to the outside of the chip, and an input section logic circuit A whose input and output are both connected to the inside logic circuit of the chip.
It can be divided into three types: B, which does not go out of the chip, and C, whose output is connected to the outside of the chip. In FIG. 3, the dotted line commonly connected to the logic circuits A and C indicates the control line of the constant current source.

第4図は第3図論理回路Aに本発明を適用した
回路構成の一実施例を示す図で、基準電圧回路は
2つの同じ特性の定電流源Q10,R10,Q11,R11
有し、1つの定電流源Q11,R11は制御端子12が
導出され、他の1つの定電流源Q10,R10はチツプ
内の定電流源基準電圧を与える定電圧に接続され
る端子11を有する。制御端子12に定電圧(制
御信号)が加えられなければトランジスタQ11
遮断状態にあるから、第4図の回路は第1図の論
理回路と同じ動作をする。即ちトランジスタQ8
のベースに接続される基準電圧は第1図の論理回
路の論理振幅の中央に設定され、小さい論理振幅
に対する基準を与える。
FIG . 4 is a diagram showing an embodiment of a circuit configuration in which the present invention is applied to the logic circuit A in FIG . One constant current source Q 11 , R 11 has a control terminal 12 led out, and the other constant current source Q 10 , R 10 is connected to a constant voltage that provides a constant current source reference voltage in the chip. It has a terminal 11. Since transistor Q11 is in a cutoff state unless a constant voltage (control signal) is applied to control terminal 12, the circuit of FIG. 4 operates in the same way as the logic circuit of FIG. 1. i.e. transistor Q 8
The reference voltage connected to the base of is set at the center of the logic swing of the logic circuit of FIG. 1 and provides a reference for small logic swings.

入力端子9又は10に加えられる論理入力電圧
が大きくなつた(例えば第4図のトランジスタ
Q6,Q7,Q8のコレクタでの論理振幅の2倍)と
すれば論理回路の基準電圧(トランジスタQ8
ベース電位)は論理“1”側にずれることにな
る。即ち論理振幅の1/4の所に基準電圧が位置す
ることになり、正しい基準電圧として動作しなく
なり、誤動作するおそれが生じる。しかし制御端
子12を定電流源基準電圧端子11に接続すると
トランジスタQ11も導通し、基準電圧を発生する
抵抗R8には今迄の2倍の電流が流れるので基準
電圧は2倍となり、入力に加えられた2倍の論理
振幅の中央に基準電圧が設定され、この論理回路
は正しく動作する。即ち入力論理信号のレベルが
大きい場合に正しい動作が可能となる。例では2
倍の入力論理振幅で考えたが、入力論理振幅は2
倍である必要がなく入力論理振幅に応じた基準電
圧を発生させるには、抵抗R11の値を変えること
で任意の基準電圧を発生できることは明らかであ
る。また抵抗R11の値を変えたくない場合は制御
端子12に加える定電圧を変えても同様な効果を
得ることができる。
The logic input voltage applied to input terminal 9 or 10 is increased (e.g. the transistor in Fig. 4).
(twice the logic amplitude at the collectors of Q 6 , Q 7 , and Q 8 ), the reference voltage of the logic circuit (base potential of transistor Q 8 ) will shift toward the logic “1” side. That is, the reference voltage will be located at 1/4 of the logic amplitude, and will no longer operate as a correct reference voltage, resulting in a risk of malfunction. However, when the control terminal 12 is connected to the constant current source reference voltage terminal 11, the transistor Q11 also becomes conductive, and twice the current flows through the resistor R8 that generates the reference voltage, so the reference voltage becomes twice as high as the input voltage. The reference voltage is set at the center of the twice the logic amplitude added to , and this logic circuit operates correctly. That is, correct operation is possible when the level of the input logic signal is high. In the example 2
I thought about double the input logic amplitude, but the input logic amplitude is 2
It is clear that any reference voltage can be generated by changing the value of the resistor R 11 in order to generate a reference voltage that does not need to be doubled and is responsive to the input logic amplitude. Furthermore, if it is not desired to change the value of the resistor R11 , the same effect can be obtained by changing the constant voltage applied to the control terminal 12.

即ち第4図の回路は制御端子12を制御するこ
とにより論理振幅の変換(レベル変換)が可能と
なることがわかる。
That is, it can be seen that the circuit shown in FIG. 4 enables logical amplitude conversion (level conversion) by controlling the control terminal 12.

第5図は第3図の出力部論理回路Cに本発明を
適用した一実施例を示す図である。この図では電
流切換回路部に2つの定電流源Q15,R15,Q16
R16を持つ構成となつている。1つの定電流源
Q15,R15には制御端子17を有し、他の定電流源
R16,R16の定電流源基準電圧端子18はチツプ内
の定電圧が与えられるものである。制御端子17
に定電圧(制御信号)が加えられていないとき
は、第5図の論理回路は第1図の論理回路に等し
い論理レベルで動作するが、制御端子17を端子
18に接続しかつ抵抗R15の抵抗値を抵抗R16の抵
抗値に等しく取れば電流切換回路部には前の状態
に比較して2倍の電流が流れ、従つて出力端子1
5又は16に現われる論理振幅も2倍となる。こ
の説明ではトランジスタQ15抵抗R15より成る定電
流回路を、トランジスタQ1抵抗R1より成る定電
流源と同じ特性として考えたが、必ずしもこの必
要はなく、出力端子15又は16に現わす論理振
幅を任意に変えることができるのは第4図につき
説明した場合と同じである。即ち第5図に於ては
制御端子17に制御信号を与えたり、外したりす
ることにより出力端子15,16の出力論理振幅
を大きくしたり小さくしたりできる。
FIG. 5 is a diagram showing an embodiment in which the present invention is applied to the output section logic circuit C of FIG. 3. In this figure, two constant current sources Q 15 , R 15 , Q 16 ,
It is configured with R 16 . one constant current source
Q 15 and R 15 have control terminals 17, and other constant current sources
Constant current source reference voltage terminals 18 of R 16 and R 16 are supplied with a constant voltage within the chip. Control terminal 17
When no constant voltage (control signal) is applied to the logic circuit of FIG. 5, the logic circuit of FIG. 5 operates at the same logic level as the logic circuit of FIG. If the resistance value of R16 is taken to be equal to the resistance value of resistor R16, twice as much current will flow through the current switching circuit compared to the previous state, and therefore output terminal 1
The logic amplitude appearing at 5 or 16 is also doubled. In this explanation, a constant current circuit consisting of a transistor Q 15 and a resistor R 15 is considered to have the same characteristics as a constant current source consisting of a transistor Q 1 and a resistor R 1 . The ability to change the amplitude arbitrarily is the same as in the case explained with reference to FIG. That is, in FIG. 5, by applying or removing a control signal to the control terminal 17, the output logic amplitudes of the output terminals 15 and 16 can be increased or decreased.

上述した本発明による半導体論理回路によれば
基準電圧が得られる抵抗R8、又は負荷抵抗R12
R13に流れる電流を、定電流源の制御端子に対す
る電圧制御信号で動作、不動作制御して、このチ
ツプに接続される外部の論理回路の論理振幅に合
せて基準電圧を大きくしたり、論理レベルを大き
くしたりすることができる。
According to the semiconductor logic circuit according to the present invention described above, the resistor R 8 from which the reference voltage is obtained, or the load resistor R 12 ,
The current flowing through R13 is controlled to be activated or deactivated using a voltage control signal sent to the control terminal of the constant current source, and the reference voltage can be increased in accordance with the logic amplitude of an external logic circuit connected to this chip, or You can increase the level.

従つてLSIチツプ内では論理回路を低電力で高
速動作させることができ、非常に小さい振幅信号
とし余分なレベル変換用チツプを使用せずに、チ
ツプ外へは論理振幅を大きくして動作させること
ができる。よつて実装密度は高まり、余分なレベ
ル変換チツプも使用しないので、コストを下げる
ことも可能である。更に本発明によるLSIチツプ
を製造することにより例えばマルチチツプLSI
(多数個のチツプを例えば相互配線されたアルミ
ナ基板上に実装してLSIを構成するもの)のよう
にアルミナ基板内では小論理振幅動作し、アルミ
ナ基板から外側では大論理振幅動作としたいとき
にも、アルミナ基板の端子に接続されているチツ
プは制御端子と定電流源基準定電圧端子を短絡す
ることにより容易に目的を達成することができる
ので異なつた論理振幅のLSIチツプを製造する必
要がなく、その経済的効果は大きい。
Therefore, logic circuits can be operated at low power and high speed inside an LSI chip, and the logic circuits can be operated with a very small amplitude signal without using an extra level conversion chip, and with a large logic amplitude outside the chip. I can do it. As a result, packaging density is increased, and since no extra level conversion chips are used, costs can be reduced. Furthermore, by manufacturing the LSI chip according to the present invention, for example, multi-chip LSI
(For example, when multiple chips are mounted on an alumina substrate interconnected to form an LSI), when you want to operate with a small logic amplitude inside the alumina substrate and operate with a large logic amplitude outside the alumina substrate. However, since the purpose of the chip connected to the terminals of the alumina substrate can be easily achieved by shorting the control terminal and the constant current source reference constant voltage terminal, it is necessary to manufacture LSI chips with different logic amplitudes. The economic effect is large.

上述においては主としてNPNトランジスタを
用いたLSIチツプにより本発明の動作を説明した
がPNPトランジスタを用いたLSIチツプにも本発
明は適用できる。またLSIチツプの入力部論理回
路、出力部論理回路の一方にのみ本発明を適用す
ることもできる。
In the above description, the operation of the present invention was mainly explained using an LSI chip using NPN transistors, but the present invention can also be applied to an LSI chip using PNP transistors. Furthermore, the present invention can be applied only to either the input logic circuit or the output logic circuit of an LSI chip.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は定電流源を使用した従来の電流切換回
路を示す接続図、第2図は基準電圧を発生する回
路図、第3図は本発明を適用した半導体論理回路
を使用したLSIチツプの論理構成を示すブロツク
図、第4図は本発明による半導体論理回路の入力
部論理回路の一実施例を示す接続図、第5図は本
発明による半導体論理回路の出力部論理回路の一
実施例を示す接続図である。 A……入力部論理回路、C……出力部論理回
路。
Figure 1 is a connection diagram showing a conventional current switching circuit using a constant current source, Figure 2 is a circuit diagram for generating a reference voltage, and Figure 3 is an LSI chip using a semiconductor logic circuit to which the present invention is applied. A block diagram showing the logical configuration, FIG. 4 is a connection diagram showing an embodiment of the input section logic circuit of the semiconductor logic circuit according to the present invention, and FIG. 5 is an embodiment of the output section logic circuit of the semiconductor logic circuit according to the present invention. FIG. A...Input logic circuit, C...Output logic circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 入力信号および基準信号をうける電流切換用
のトランジスタ対と、該トランジスタ対の各一端
と第1の電源との間に夫々接続された負荷回路
と、前記トランジスタ対の各他端を共通に接続
し、その接続点と第2の電源との間に夫々並列に
接続された第1および第2の定電流回路と、前記
トランジスタ対の前記一端から出力を取り出す手
段とを同一半導体基板上に有し、前記第1の定電
流回路は前記半導体基板上で作られる内部信号に
応答して常時動作し、前記第2の定電流回路は前
記半導体基板の外側から入力される信号に応答し
て、前記トランジスタ対の前記一端から取り出さ
れる出力の振幅レベルを通常のレベルと異ならし
める時動作するように制御されることを特徴とす
る半導体論理回路。
1. A pair of current switching transistors receiving an input signal and a reference signal, a load circuit connected between one end of each of the pair of transistors and a first power source, and the other end of the pair of transistors connected in common. and a first and second constant current circuit connected in parallel between the connection point and a second power supply, and means for taking out an output from the one end of the transistor pair, on the same semiconductor substrate. The first constant current circuit always operates in response to an internal signal generated on the semiconductor substrate, and the second constant current circuit responds to a signal input from outside the semiconductor substrate. A semiconductor logic circuit characterized in that it is controlled to operate when the amplitude level of an output taken out from the one end of the transistor pair is made to be different from a normal level.
JP57004369A 1982-01-14 1982-01-14 Semiconductor logical circuit Granted JPS57136820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57004369A JPS57136820A (en) 1982-01-14 1982-01-14 Semiconductor logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57004369A JPS57136820A (en) 1982-01-14 1982-01-14 Semiconductor logical circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP47044072A Division JPS597247B2 (en) 1972-05-01 1972-05-01 semiconductor logic circuit

Publications (2)

Publication Number Publication Date
JPS57136820A JPS57136820A (en) 1982-08-24
JPS6126252B2 true JPS6126252B2 (en) 1986-06-19

Family

ID=11582450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57004369A Granted JPS57136820A (en) 1982-01-14 1982-01-14 Semiconductor logical circuit

Country Status (1)

Country Link
JP (1) JPS57136820A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142619A (en) * 1983-12-28 1985-07-27 Fujitsu Ltd Semiconductor integrated circuit

Also Published As

Publication number Publication date
JPS57136820A (en) 1982-08-24

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