JPS61201329A - 並列アレイ乗算器 - Google Patents

並列アレイ乗算器

Info

Publication number
JPS61201329A
JPS61201329A JP4226685A JP4226685A JPS61201329A JP S61201329 A JPS61201329 A JP S61201329A JP 4226685 A JP4226685 A JP 4226685A JP 4226685 A JP4226685 A JP 4226685A JP S61201329 A JPS61201329 A JP S61201329A
Authority
JP
Japan
Prior art keywords
array
multiplier
array multiplier
carry
multipliers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4226685A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0416810B2 (fr
Inventor
Shigeo Daito
大東　栄夫
Koji Sakamoto
康治 坂本
Itaru Kurosawa
格 黒沢
Toshio Tsurushima
鶴島　稔夫
Hisao Tagami
尚男 田上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP4226685A priority Critical patent/JPS61201329A/ja
Publication of JPS61201329A publication Critical patent/JPS61201329A/ja
Publication of JPH0416810B2 publication Critical patent/JPH0416810B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
JP4226685A 1985-03-04 1985-03-04 並列アレイ乗算器 Granted JPS61201329A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4226685A JPS61201329A (ja) 1985-03-04 1985-03-04 並列アレイ乗算器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4226685A JPS61201329A (ja) 1985-03-04 1985-03-04 並列アレイ乗算器

Publications (2)

Publication Number Publication Date
JPS61201329A true JPS61201329A (ja) 1986-09-06
JPH0416810B2 JPH0416810B2 (fr) 1992-03-25

Family

ID=12631232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4226685A Granted JPS61201329A (ja) 1985-03-04 1985-03-04 並列アレイ乗算器

Country Status (1)

Country Link
JP (1) JPS61201329A (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6479862A (en) * 1987-09-21 1989-03-24 Agency Ind Science Techn Semiconductor integrated circuit device
JPH03105808U (fr) * 1990-02-19 1991-11-01
JPH0644050A (ja) * 1991-03-11 1994-02-18 Agency Of Ind Science & Technol 積和演算装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6479862A (en) * 1987-09-21 1989-03-24 Agency Ind Science Techn Semiconductor integrated circuit device
JPH03105808U (fr) * 1990-02-19 1991-11-01
JPH0644050A (ja) * 1991-03-11 1994-02-18 Agency Of Ind Science & Technol 積和演算装置

Also Published As

Publication number Publication date
JPH0416810B2 (fr) 1992-03-25

Similar Documents

Publication Publication Date Title
KR940002479B1 (ko) 고속 디지탈 병렬승산기(multiplier)
Oklobdzija et al. Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology
US4525797A (en) N-bit carry select adder circuit having only one full adder per bit
JPH10111790A (ja) 演算セル
JPH0934688A (ja) 遅延整合技術の利用によりクリティカル・パスを減少させた浮動小数点型掛け算器及びその演算方法
JPH0456339B2 (fr)
Lin Reconfigurable parallel inner product processor architectures
US6275841B1 (en) 1-of-4 multiplier
US5291431A (en) Array multiplier adapted for tiled layout by silicon compiler
Samavi et al. Modular array structure for non-restoring square root circuit
Wang et al. A nano-scale design of Vedic multiplier for electrocardiogram signal processing based on a quantum technology
Verma et al. Design and analysis of efficient vedic multiplier for fast computing applications
US5974437A (en) Fast array multiplier
JPS61201329A (ja) 並列アレイ乗算器
Cheng A minimum test set for multiple fault detection in ripple carry adders
Baddam et al. Divided backend duplication methodology for balanced dual rail routing
Mokrian et al. On the use of 4: 2 compressors for partial product reduction
Suryawanshi et al. Vedic Multiplier Using Carry look ahead adder
CN106020768B (zh) 用于高基数乘法器电路的组合的加法器和预加法器
Chouhan et al. Implementation of an efficient multiplier based on Vedic mathematics using high speed adder
JP2700876B2 (ja) 並列乗算器
Primlani et al. A nonredundant-radix-4 serial multiplier
JPH0370416B2 (fr)
JP4502662B2 (ja) 乗算器−累算器ブロックモード分割
JPH0644050A (ja) 積和演算装置

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term