JPS61229366A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices such as MO3 field effect transistors.

[Conventional technology]

Generally, as shown in FIGS. 6 and 7, a field effect transistor includes a semiconductor substrate 2 of one conductivity type, such as N-type silicon, and a p-well (well) as a conductive region of the opposite conductivity type.
l) 4 is formed, and in this p-well 4, a source region 6 and a drain region 8 of the opposite conductivity type to that of the p-well 4 are formed at regular intervals, and between these source region 6 and drain region 8, A channel region 10 is formed therein. The surfaces of the semiconductor substrate 2, p-well 4, source region 6, and drain region 8 are covered with an oxide film 12, and a source electrode 14 and a drain electrode 16 are formed on the surfaces of the source region 6 and drain region 80. The oxide film 13 covering the channel region 10 is set thinner than other parts, and a gate electrode 18 is formed on the surface of this thin oxide film 13 by vapor deposition of aluminum or the like.

[Problem that the invention seeks to solve]

Conventionally, in such a field effect transistor, the portions on the surface of the semiconductor substrate 2 where the source region 6, drain region 8, and channel region 10 are formed are not considered.
Since the p-well 4 is formed by indiscriminate impurity diffusion or ion implantation, the center of the p-well 4 and its surface layer have the highest impurity concentration, and a concentration gradient is exhibited in the plane direction and depth direction. . That is, the impurity concentration of the channel region 10 and the impurity concentrations near the source region 6 and drain region 8 have a uniform profile.

For this reason, in this type of field effect transistor, electrical characteristics such as frequency characteristics, breakdown voltage, and dark voltage vtn are fixed, making it difficult to set these characteristics arbitrarily, and devices with different characteristics can be integrated into the same semiconductor. It could not be formed arbitrarily on the substrate.

Furthermore, in the conventional device, since the impurity concentration in the channel region 10 is uniform, the semiconductor device becomes bidirectional, and the directionality cannot be set.

Therefore, this invention provides frequency characteristics, breakdown voltage, dark value voltage VT
The present invention aims to provide a semiconductor device in which electrical characteristics such as H can be arbitrarily set and which has directionality.

[Means for Solving the Problems] The present invention will be described with reference to the embodiments shown in FIGS. 1 and 2.

That is, a source region 26 and a drain region 28 are provided in a conductive region (p well 22) of an opposite conductivity type provided in a semiconductor substrate 20 of a -conductivity type. A channel region 24 is formed between the source region 26 and the drain region 28, and a gate electrode 38 faces the channel region 24.

'In such a semiconductor device, the impurity concentration of the channel region 24 has a gradient, and a region 22a with a low impurity concentration and a region 22b with a high impurity concentration are formed.

[For production]

With such a configuration, the impurity concentration in the channel region 24 has a gradient and the impurities are distributed, thereby producing a drift effect according to the impurity concentration distribution, improving the frequency characteristics and breakdown voltage, and improving the directionality. occurs.

〔Example〕

Embodiments of the semiconductor device of the present invention will be described in detail below with reference to the drawings.

1 and 2 show an embodiment of the semiconductor device of the present invention, with FIG. 1 showing its planar structure, and FIG. 2 showing its cross section along the line ■-■.

1 and 2, a p-well 22 as a conductive region of an opposite conductivity type is formed from two directions on a semiconductor substrate 20 of one conductivity type such as N-type silicon. A source region 26 and a drain region of a conductivity type opposite to that of the p-well 22 are formed so that the channel region 24 spans a region 22a with a low impurity concentration and a region 22b with a high impurity concentration in the almost central region of the p-well 22. 28 is formed.

In this embodiment, 'p' is located in the center of the channel region 24.
A peripheral portion from one side of the well 2 is placed, and the impurity concentration changes around the channel region 24.

The surfaces of the semiconductor substrate 20, p-well 22, source region 26, and drain region 28 are covered with an oxide film 30, and a source electrode 32 and a drain electrode 34 are formed on the surfaces of the source region 26 and drain region 28. ing.

The oxide film 36 covering the channel region 24 is set thinner than other parts, and a gate electrode 38 is formed on its surface by vapor deposition of aluminum or the like.

In this way, the channel region 2 is a region where the impurity concentration distribution of the conductive region constituting the p-well 22 changes stepwise.
If you set it to 4, you can get a corresponding drift effect,
In addition to improving electrical characteristics such as frequency characteristics and dynamic breakdown voltage, the device is configured as a unidirectional semiconductor device instead of the conventional bidirectional one.

Next, a method of manufacturing a semiconductor device according to the present invention will be explained with reference to FIGS. 3 to 5.

That is, this embodiment shows a case where the p-well 22 is formed by diffusion of impurities, and as shown in FIG. 3, a resist film 40 is formed on the surface of the semiconductor substrate 20 to cover the surface. An opening 42 for impurity diffusion is selectively formed in the resist film 40. In this case, the portion that will become the channel region is covered with a resist film 40, an opening 42 is formed around the resist film 40, and the semiconductor substrate 2 is opened from the opening 42.
Impurity atoms such as boron are diffused into the surface layer of 0.

Regarding the diffusion state of impurities, as shown in FIG. 4, the impurity concentration decreases as the distance from the opening 42 increases. in this case,
At the peripheral edge of the p-well 22, the impurities diffused from the openings 42 on both sides overlap, but the impurity concentration decreases as the distance from the opening 42 increases, so that it is lower than directly below the opening 42, and the amount of impurity diffused is and opening 42
The impurity concentration of the portion that becomes the channel region can be controlled by the position of the channel region.

After the p-well 22 is formed by controlling the impurity concentration locally in this way, the region of the p-well 22 where a specific impurity concentration is obtained becomes the channel region 24, as shown in FIG. As such, source region 26 and drain region 28 are formed according to conventional manufacturing processes.

Then, a semiconductor substrate 20, a p-well 22, a source region 2
6 and the oxide film 3 formed on the surface of the drain region 28
A source electrode 32 and a drain electrode 34 are formed in the source region 26 and drain region 28 of No. 0, respectively, and a channel region is formed.

A gate electrode 38 is formed on the surface of the oxide film 36 covering the oxide film 24, and the semiconductor device shown in FIGS. 1 and 2 is obtained.

In this semiconductor device, the channel region 2 of the p-well 22
The impurity concentration of the portion set to 4 can be arbitrarily controlled, and the control can be performed partially at a desired position on the same semiconductor substrate, and electrical characteristics such as frequency characteristics, dark value, and breakdown voltage can be controlled. Products with different characteristics can be obtained at the same time.

In this embodiment, the p-well 22 was formed by impurity diffusion, but the p-well 22 may also be formed by ion implantation.

Further, in the embodiment, a case has been described in which a p-well is formed in an N-type semiconductor substrate, but the present invention can be similarly applied to a case in which an n-well is formed in a P-type semiconductor substrate.

〔Effect of the invention〕

As explained above, according to the present invention, since the impurity concentration distribution in the channel region is varied in stages, a drift effect can be obtained, and electrical characteristics such as frequency characteristics and breakdown voltage can be improved, and directionality can be improved. It is also possible to configure devices with different electrical characteristics such as threshold values, frequency characteristics, and breakdown voltages on the same semiconductor substrate.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing a planar structure of an embodiment of a semiconductor device of the present invention, FIG. 2 is a cross-sectional view taken along the line nn in FIG. 1, and FIG. 3 shows a resist film installed on a semiconductor substrate and its FIG. 4 is a plan view showing the opening, FIG. 4 is a cross-sectional view showing the situation of impurity diffusion, FIG. 5 is a cross-sectional view showing another example of impurity diffusion, and FIG.
The figure is a plan view showing the electrode arrangement of a general field effect transistor, and FIG. 7 is a cross-sectional view taken along the line ■--■ in FIG. 6. 20...Semiconductor substrate, 22...P as a conductive region
Well, 22a... portion with low impurity concentration, 22b...
... portion with high impurity concentration, 24 ... channel region, 26 ... source region, 28 ... drain region, 3
8...Gate electrode. 113 Figure $4 Cause Figure 5

Claims (1)

[Claims] In a semiconductor device in which a source region and a drain region are provided in a conductive region of an opposite conductivity type provided on a semiconductor substrate of one conductivity type, and a gate is made to face a channel region formed between the source region and the drain region. . A semiconductor device characterized in that the impurity concentration of the channel region has a gradient.