JPS61240352A - Interface-signal reading system - Google Patents

Abstract

PURPOSE:To reduce processing load by so forming the titled system that a processor actuates an interruption processing program and executes the read of an interface information only when an interruption request signal is made. CONSTITUTION:When the interface information varies, a dissidence is generated between the input and output in flip-flop circuits FF1-FF4 that correspond to the said variation of the information. The dissidence is detected by a correspondent exclusive OR circuits EOR1-EOR4, and is transmitted to an interruption processing circuit 16 of a central processing unit 11. On receiving the dissidence signal from a comparator circuit 13, the circuit 16 informs an interruption processing signal to the processor 14, and the processing of reading the interface information is executed. At this processing, as the processor 14 reads out the interface information through a read circuit 12, the input and output in the FF1-FF4 become coincident, and the dissidence output is nullified, and the interruption signal also is automatically made invalid.

Description

[Detailed Description of the Invention] [Summary] An interface signal reading method that includes an interface circuit for reading the state of a peripheral device and performs processing to monitor the output of the interface circuit, that is, changes in the state of the peripheral device. , if there is a mismatch between the previously read interface information and the current interface information, an interrupt is generated to the processing device to notify the processing device that there has been a change in the interface information, and the device performs a reading operation. It is something.

[Industrial application field]

The present invention relates to an interface signal reading method,
More specifically, the present invention relates to an interface information reading method for an information processing system, which includes an interface circuit for reading the state of a peripheral device, detects a change in information indicating the state of the peripheral device, and executes the readout. be.

In an information processing system, when the central control unit CPU reads the state of a peripheral device and performs processing, when the state of the peripheral device changes, it is necessary to read this change and perform processing.

The present invention relates to a method for reading and processing such changes.

[Conventional technology]

In an information processing system, a circuit as shown in FIG. 2 has conventionally been used as a circuit for reading interface information.

In FIG. 2, 1 is a central processing unit, 2 is a processing unit, and 3 is a central processing unit.
indicate a common data bus, respectively.

The processing device 2 is constituted by an IC as a data bus buffer, for example.

In the circuit shown in FIG. 2, the processing unit 2 scans the interface signal according to a command from the central processing unit 1, and writes the state of the interface detected during scanning into the memory of the central processing unit 1 via the common data bus 3. , changes in the interface information were detected by comparing the currently detected interface information with the information previously written to memory.

[Problem that the invention seeks to solve]

In the conventional processing system as shown in FIG. 2, the processing device 2 reads out the interface circuit at regular intervals to detect changes in the interface information. As described above, it is necessary to supervise and process interface signals at regular intervals, resulting in a heavy processing load and impeding processing efficiency.

An object of the present invention is to eliminate serious drawbacks in interface reading, reduce the processing load on a processing unit when reading interface information into a central processing unit, and improve the processing efficiency of the central processing unit.

[Means for solving problems]

The present invention includes a memory circuit that inputs interface information from a peripheral device, holds it, and outputs it, a comparison circuit that uses the input and output of the memory circuit as two inputs, and a readout circuit that reads the output of the memory circuit. Be equipped.

The comparison circuit compares the mismatch between the input signal and the output signal of the storage circuit that occurs when the interface information changes, and sends the mismatch comparison output as an interrupt request signal to the readout circuit. An interrupt processing program is activated by the interrupt request signal to execute reading of the interface information.

[For production]

The processing unit starts the interrupt processing program and reads the interface information only when an interrupt request signal is received from the central processing unit, eliminating the need for reading at regular intervals as in the past, and processing Reduce the processing load on the device.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of the register configuration method of the present invention.

In FIG. 1, 11 is a central processing unit, 12 is a storage circuit, 13 is a comparison circuit, 14 is a processing device, 15 is a common data bus, and 16 is an interrupt processing circuit.

The memory circuit 12 includes, for example, flip-flop circuits FF1 . FFz
, FFs, and FFa, and the comparator circuit 13 is an exclusive OR circuit EOR whose inputs and outputs are the inputs and outputs of the flip-flops FF+, FFz, FPs, and FFa.
,.

! ! The processing device 14 is composed of an ORt, an EORs, an IEOR4, and an OR circuit OR, and a data bus buffer DBD.

It is composed of DBDz, DBD3, and DBD4.

In the circuit shown in Figure 1, the flip-flop circuits FF and -FF are first cleared, and then when interface information is input, that information is held and latched in FF+ -FF4, and its output is sent to the data bus buffer of the readout circuit. Sent to DBDI-DBDO.

When the interface information changes, a mismatch occurs between the input and output of the flip-flop circuit (FF, to FF4) corresponding to the changed information, and this mismatch causes the corresponding exclusive-OR circuit (EOR).

~EOR4), and the detected output is sent to the interrupt processing circuit 16 of the central processing unit 1 via the OR circuit OR.
sent to.

When the interrupt processing circuit 16 receives the mismatch signal from the comparison circuit 13, it notifies the processing device 14 of the interrupt processing signal. As a result, the processing device 14 performs a process of reading out the interface information. Through this reading process, the processing device 14 reads the interface information via the storage circuit 12, and at the same time,
As a result of the read operation, the inputs and outputs of the flip-flop circuits (FF, to FF#) of the storage circuit 12 match, the mismatched outputs are invalidated, and the interrupt signal is also automatically invalidated.

〔Effect of the invention〕

As described in detail above, according to the present invention, the processing device does not need to constantly monitor (scan) the state of the interface information at regular intervals, and the processing device only uses an interrupt when there is a change in the interface state. It is only necessary to notify the interface and perform the interface reading process, which reduces the processing load for reading and allows the processing power saved due to this to be allocated to other things.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the interface signal reading method of the present invention, and FIG. 2 is a block diagram of a conventional method for detecting changes in interface information. In FIG. 1, 11 is a central processing unit; 12 13 is a storage circuit, 13 is a comparison circuit, 14 is a readout circuit, 15 is a common data bus, and 16 is an interrupt processing circuit. Interface signals Block diagram of the method of the present invention Figure 1 Interface signals Figure 2

Claims (1)

[Scope of Claims] An information processing system that includes an interface circuit for reading the state of a peripheral device and detects and processes changes in interface information that is an output of the interface circuit, comprising: inputting and retaining the interface information; The storage circuit further includes a storage circuit that outputs, a comparison circuit that uses the input and output of the storage circuit as two inputs, and a readout circuit that reads the output of the storage circuit, and the storage circuit that is generated when the interface information changes. The comparison circuit compares the mismatch between the input signal and the output signal, and sends the mismatch comparison output as an interrupt request signal to the readout circuit, and the readout circuit starts an interrupt processing program by the interrupt request signal. ,
An interface signal reading method characterized by reading out the interface information.