JPS61253U - 自己整列ゲートｃｍｏｓ装置 - Google Patents

自己整列ゲートｃｍｏｓ装置

Info

Publication number
JPS61253U
JPS61253U JP1985074930U JP7493085U JPS61253U JP S61253 U JPS61253 U JP S61253U JP 1985074930 U JP1985074930 U JP 1985074930U JP 7493085 U JP7493085 U JP 7493085U JP S61253 U JPS61253 U JP S61253U
Authority
JP
Japan
Prior art keywords
oxide layer
region
masking
conductivity type
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985074930U
Other languages
English (en)
Inventor
グレゴリオ・スパデア
Original Assignee
ナシヨナル・セミコンダクター・コーポレーシヨン
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ナシヨナル・セミコンダクター・コーポレーシヨン filed Critical ナシヨナル・セミコンダクター・コーポレーシヨン
Publication of JPS61253U publication Critical patent/JPS61253U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/858—Complementary IGFETs, e.g. CMOS comprising a P-type well but not an N-type well
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/07—Guard rings and cmos
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図〜第６図は本考案の自己整列ゲートＣＭＯＳを製
作工程順に示す断面図、第７図〜第１１図は本考案の別
の自己整列ゲー｝ＣＭＯＳを製作工程順に示す断面図、
第１２図〜第１５図は、第１図〜第６図の装置を修正し
た形態の自己整列ゲ−トｃＭＯｓを製作工程順に示す断
面図、第１６図〜第１９図は本考案のさらに別の自己整
列ゲートＣＭＯＳを製作工程順に示す断面図である。 １２二酸化ケイ素、１３：Ｎ基板、１４：Ｐ一領域、１
５：酸化物ゲート層、１６：窒化ケイ素、１７．１７’
：Ｐ＋ソースドレイン領域、１８：Ｐ＋ガードリング、
１９：酸化ケイ素、２１．２１’：Ｎ＋ソースドレイン
領域、２２：Ｎ＋ガードリング、２３二酸化ケイ素、２
４：接触孔、２５：金属接点、３１：ケイ素Ｎ層、３２
：絶縁基板、３４：窒化ケイ素、３５：Ｐ十領域、３６
：酸化ケイ素、３７：フォトレジスト、３８：孔、３９
：Ｐ一領域、４２：Ｎ＋ソースドレイン領域、４３：酸
化ケイ素、４４：金属接点、４５：ゲート電極、５１：
フォトレジスト。

Claims (1)

    【実用新案登録請求の範囲】
  1. 第１の電導型の半導体基板の表面上に第１の酸化物層を
    形成し、この第１の酸化物層をマスキングした後、エッ
    チングして第１の酸化物層中の陪基板の第１領域に達す
    る孔を形成し、この第１領域にドニプ剤を拡散させて該
    基板中に第２の電導型の領域を形成し、第１の酸化物層
    の残りを除去し、基板の表面上に第２の酸化物層を形成
    し、この第２の酸化物層の上に窒化ケイ素層を形成し、
    この窒化ケイ素と第２の化物層をマスキングおよびエッ
    チングして、これに前記第１領域と離して孔を形成し、
    この孔を通してドープ剤を拡散させて基板内に前記の第
    ２の電導型のソースおよびドレイン領域を形成し、窒化
    ケイ素と第２の酸化物層をマスキングおよびエッチング
    して前記第１領域上に孔を形成し、この孔を通してドー
    プ剤を拡散させて前記第１領域に前記第１の電導型のソ
    ースおよびドレイン領域を形成し、酸化ケイ素層の各ソ
    ースおよびドレイン領域の上に当る部分をマスキングお
    よびエッチングして前記領域への接触孔を形成し、ゲー
    ト領域の窒化ケイ素層をエッチングで除去し、装置上に
    金属化層を沈着させ、この金属層中に金続接続および接
    続孔を区画するためにマスキングし、金属をエッチング
    してゲート電極とソースおよびドレイン接続子を形成し
    て成ることを特徴とする自己整列ゲー｝ＣＭＯＳ装置。
JP1985074930U 1975-05-08 1985-05-20 自己整列ゲートｃｍｏｓ装置 Pending JPS61253U (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/575,655 US3983620A (en) 1975-05-08 1975-05-08 Self-aligned CMOS process for bulk silicon and insulating substrate device
US575655 1995-12-20

Publications (1)

Publication Number Publication Date
JPS61253U true JPS61253U (ja) 1986-01-06

Family

ID=24301188

Family Applications (2)

Application Number Title Priority Date Filing Date
JP51052760A Pending JPS51138174A (en) 1975-05-08 1976-05-08 Method of producing selffarrangement cmos to bulk silicon and insulating substrate device
JP1985074930U Pending JPS61253U (ja) 1975-05-08 1985-05-20 自己整列ゲートｃｍｏｓ装置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP51052760A Pending JPS51138174A (en) 1975-05-08 1976-05-08 Method of producing selffarrangement cmos to bulk silicon and insulating substrate device

Country Status (6)

Country Link
US (1) US3983620A (ja)
JP (2) JPS51138174A (ja)
CA (1) CA1057862A (ja)
DE (4) DE2661098C2 (ja)
FR (1) FR2310635A1 (ja)
GB (4) GB1529298A (ja)

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US4061530A (en) * 1976-07-19 1977-12-06 Fairchild Camera And Instrument Corporation Process for producing successive stages of a charge coupled device
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US4402002A (en) * 1978-04-06 1983-08-30 Harris Corporation Radiation hardened-self aligned CMOS and method of fabrication
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Also Published As

Publication number Publication date
FR2310635A1 (fr) 1976-12-03
JPS51138174A (en) 1976-11-29
CA1057862A (en) 1979-07-03
DE2620155C2 (ja) 1988-05-19
DE2661099C2 (ja) 1988-10-20
GB1529296A (en) 1978-10-18
GB1529298A (en) 1978-10-18
DE2620155A1 (de) 1976-11-18
GB1529023A (en) 1978-10-18
DE2661098C2 (ja) 1989-07-06
DE2661097C2 (ja) 1988-05-26
GB1529297A (en) 1978-10-18
US3983620A (en) 1976-10-05
FR2310635B1 (ja) 1980-02-15

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