JPS6142878U - Mounting structure of semiconductor device for watch - Google Patents

Mounting structure of semiconductor device for watch

Info

Publication number
JPS6142878U
JPS6142878U JP1985114666U JP11466685U JPS6142878U JP S6142878 U JPS6142878 U JP S6142878U JP 1985114666 U JP1985114666 U JP 1985114666U JP 11466685 U JP11466685 U JP 11466685U JP S6142878 U JPS6142878 U JP S6142878U
Authority
JP
Japan
Prior art keywords
chip
semiconductor device
watch
mounting structure
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985114666U
Other languages
Japanese (ja)
Inventor
芳夫 飯沼
條平 済木
明道 鷺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP1985114666U priority Critical patent/JPS6142878U/en
Publication of JPS6142878U publication Critical patent/JPS6142878U/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/681Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills

Landscapes

  • Electric Clocks (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図面は本考案の一実施例を示し、第1図は断面図、第2
図はICチップと耐熱性プリント基板間のボンデイング
後の距離1と剥離強度の関係を示すグラフである。 1・・・耐熱性プリント基板、2・・・ICチップ、2
a・・・半田バンプ、3・・・エポキシ樹脂。
The drawings show one embodiment of the present invention, with FIG. 1 being a sectional view and FIG.
The figure is a graph showing the relationship between the distance 1 after bonding between the IC chip and the heat-resistant printed circuit board and the peel strength. 1... Heat-resistant printed circuit board, 2... IC chip, 2
a...Solder bump, 3...Epoxy resin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 通常のりフロー処理により、ICチップの2倍以上の熱
膨張係数を有する耐熱性プリント基板に該ICチップが
フエイスダウンボンデイングされ、且つ、少くともIC
チップ表面及び側面が樹脂蕃一ルドされている小型の時
計用半導体装置の実装構造において、前記ICチップの
半田バンプの大きさを該ICチップの大きさに応じて形
成することにより、該ICチップの大きさと前記耐熱性
プリント基板と前記ICチップとの間隔をチップ面積が
1〜4mm2のICのとき60μm以上に設定し、チッ
プ面積が4〜3m m”のICのとき80μm以上に設
定し、チップ面積が16〜35mm2のICのとき12
0μm以上に設定配置したことを特徴とする小型の時計
用半導体装置の実装構造。
The IC chip is face-down bonded to a heat-resistant printed circuit board having a coefficient of thermal expansion twice or more that of the IC chip by normal glue flow processing, and at least
In the mounting structure of a small watch semiconductor device in which the chip surface and side surfaces are covered with resin, the size of the solder bumps of the IC chip is formed according to the size of the IC chip. and the distance between the heat-resistant printed circuit board and the IC chip are set to 60 μm or more for an IC with a chip area of 1 to 4 mm, and set to 80 μm or more for an IC with a chip area of 4 to 3 mm, 12 for an IC with a chip area of 16 to 35 mm2
A mounting structure for a small semiconductor device for a watch, characterized by a set arrangement of 0 μm or more.
JP1985114666U 1985-07-26 1985-07-26 Mounting structure of semiconductor device for watch Pending JPS6142878U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985114666U JPS6142878U (en) 1985-07-26 1985-07-26 Mounting structure of semiconductor device for watch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985114666U JPS6142878U (en) 1985-07-26 1985-07-26 Mounting structure of semiconductor device for watch

Publications (1)

Publication Number Publication Date
JPS6142878U true JPS6142878U (en) 1986-03-19

Family

ID=30673677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985114666U Pending JPS6142878U (en) 1985-07-26 1985-07-26 Mounting structure of semiconductor device for watch

Country Status (1)

Country Link
JP (1) JPS6142878U (en)

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