JPH0167746U - - Google Patents
Info
- Publication number
- JPH0167746U JPH0167746U JP1987162909U JP16290987U JPH0167746U JP H0167746 U JPH0167746 U JP H0167746U JP 1987162909 U JP1987162909 U JP 1987162909U JP 16290987 U JP16290987 U JP 16290987U JP H0167746 U JPH0167746 U JP H0167746U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wiring board
- flip
- utility
- registration request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
第1図は本考案の一実施例を示すICと、これ
を実装するためのプリント基板の要部を示す側断
面図、第2図は上記両者を接合した状態を示す側
断面図、第3図は多重膜の層構成の例を示す図で
ある。
1:IC、2:IC1のパツド、3;IC1の
保護層、4:多重膜、5:プリント基板、6:プ
リント基板5のパツド、7:プリント基板の保護
層、8:半田バンプ。
Fig. 1 is a side sectional view showing an IC according to an embodiment of the present invention and the main parts of a printed circuit board for mounting the IC, Fig. 2 is a side sectional view showing a state in which the above two are joined, and Fig. The figure is a diagram showing an example of the layer structure of a multilayer film. 1: IC, 2: Pad of IC1, 3: Protective layer of IC1, 4: Multilayer film, 5: Printed circuit board, 6: Pad of printed circuit board 5, 7: Protective layer of printed circuit board, 8: Solder bump.
Claims (1)
う半導体装置において、半田バンプは前記配線基
板側にのみ形成し、半導体装置のボンデイングパ
ツドには、金属多重層のみを形成したことを特徴
とする半導体装置。 1. A semiconductor device in which flip-chip bonding is performed on a wiring board, characterized in that solder bumps are formed only on the wiring board side, and only metal multilayers are formed on bonding pads of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987162909U JPH0167746U (en) | 1987-10-23 | 1987-10-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987162909U JPH0167746U (en) | 1987-10-23 | 1987-10-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0167746U true JPH0167746U (en) | 1989-05-01 |
Family
ID=31447164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987162909U Pending JPH0167746U (en) | 1987-10-23 | 1987-10-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0167746U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04282836A (en) * | 1990-10-22 | 1992-10-07 | Internatl Business Mach Corp <Ibm> | Improvement of barrier in thin film laminate |
-
1987
- 1987-10-23 JP JP1987162909U patent/JPH0167746U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04282836A (en) * | 1990-10-22 | 1992-10-07 | Internatl Business Mach Corp <Ibm> | Improvement of barrier in thin film laminate |
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