JPS6323445A - Communication control equipment - Google Patents

Abstract

PURPOSE:To shorten the DMA transfer time by detecting a parity error after a write signal is outputted to a communication control circuit and generating an abort pattern when the parity error is detected so as to make its frame invalid. CONSTITUTION:In order to prevent a frame including an erroneous data from being sent as an effective frame even if the erroneous data is written in a communication control circuit 3, a parity error is detected after the output of a write signal and the abort pattern is generated to make the frame invalid at the detection of parity error. In detecting a parity error, an abort pattern generating circuit 5 generates >=7 consecutive data and if such a pattern exists in a frame, it is regarded as the abort pattern to make the frame invalid. Thus, a write signal is outputted before the parity error is detected, the time for DMA transfer is reduced and before the write data is converted into a serial data, the abort pattern is outputted, then no erroneous data is sent.

Description

[Detailed description of the invention] (Summary) IDLC (High Level data 1.in
a communication control circuit that enables communication of procedures (K Control), a memory with a parity bit, and a DMA (Di Control) that controls data transfer between the communication control circuit and the memory.
rect memory access) A communication control device equipped with a transfer control circuit, wherein the communication control circuit is provided with a circuit that generates an abort pattern in response to a parity error signal, and the DMA transfer control circuit sends a write signal to the communication control circuit. Detects parity error after outputting
When a parity error is detected, the abort pattern is generated to invalidate the frame, thereby shortening the DMA transfer time.

[Industrial application field]

The present invention relates to a communication control device, and more particularly, to a DMA transfer control circuit that transfers data from a memory to a communication control circuit at high speed while preventing erroneous data transmission due to paris and tie errors.

[Traditional technique]

Data from conventional memory with parity bit to communication control circuit D? When performing '1A' transfer, the method used was to confirm that no parity errors had occurred in the data read from memory before writing it to the communication control circuit. This is shown in FIG.

In FIG. 5, a data request signal is output from the communication control circuit at time t1, and when the DMA transfer control circuit outputs a read signal to the memory at time t2, the memory outputs data at time t3, and at time t4. Detect parity errors. If no parity error has occurred, a write signal is output to the communication control circuit at the time, and if a parity error has occurred, no write signal is output. At time 1b, the write signal is negated and the DMA transfer cycle ends.

This is to prevent the communication control circuit from sending out incorrect data as transmission data.

[Problem that the invention seeks to solve]

However, with this DMA transfer method, the write operation to the communication control circuit begins after securing time to confirm that no parity errors have occurred in the data read from the memory, which slows down the DI'lA transfer. There is a drawback. That is, in FIG. 5, extra time is taken from time t to time t for parity error detection.

The present invention was created in view of these points.
It is an object of the present invention to provide a communication control device that has a simple configuration and shortens DMA transfer time.

[Means and effects for solving the problems] The present invention addresses the following three points in a communication control device, namely (a) HDLC procedure is a data block unit called a frame between a start flag and an end flag. (1) The HDLC procedure has an abort pattern, and sending the abort pattern invalidates the frame being sent. (2) After the communication control circuit receives the data signal, the serial data Taking advantage of the fact that there is time to convert and send out the data, a parity error is written to prevent the frame containing the data from being sent out as a valid frame even if incorrect data is written to the communication control circuit. It is detected after a signal is output, and when a parity error is detected, an abort pattern is generated to invalidate the frame.

〔Example〕

FIG. 1 is a diagram showing one embodiment of a communication control device of the present invention.

In FIG. 1, 1 is a DMA transfer control circuit, 2 is a memory,
3 is a communication control circuit, 4 is a parity error detection circuit, and 5 is an abort pattern generation circuit.

In the apparatus shown in FIG. 1, a frame in the HDLC procedure is structured as shown in FIG. In Figure 2,
11 is a start flag, 12 is an end flag, 13 is data,
14 indicates a CRC code, and the flag is configured as six consecutive "1's" as shown in the figure.

When the abort pattern generating circuit in FIG. 1 detects a parity error, it generates seven or more consecutive patterns as shown in the figure, and if such a pattern is present in a frame, it is regarded as an abort pattern and the frame is invalidated.

The communication control circuit 3 converts parallel data into serial data, and FIG. 3 is a timing chart illustrating its operation. In Figure 3, (al is the first
Data transfer request signal in the figure, (b) is a write signal,
(C) is the write data (parallel data) read from memory 2, (di is the sending data (serial data)
are shown respectively. It takes some time for the communication control circuit 3 to convert parallel data into serial data and output it after it is written. This time is used to detect parity errors.

FIG. 4 shows a timing chart illustrating the operation of the apparatus shown in FIG. 1. In FIG. 4, (al is the communication control circuit 3
D) Data transfer request signal to IA transfer control circuit 1,
(b) is b? 'lA transfer control circuit 1 to memory 2 - Doi word, (C1 is parallel data successively output from memory 3, (dl is parity error detection timing by parity error detection circuit 4, (e) DMA transfer control circuit 1 indicates a write signal to the communication control circuit 3, (f) indicates a parity error detection signal, and (gl indicates serial transmission data).

As shown in the timing chart of FIG. 4, in this embodiment, the write signal is output before a parity error is detected, so the DMA transfer time is shortened.

Furthermore, even if a parity error occurs, that is, even if there is erroneous data, an abort pattern is output before the written data is converted to serial data, so erroneous data will not be sent.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to shorten the DMA transfer time with a simple configuration, which is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a communication control device according to the present invention, FIG. 2 is a configuration diagram of a frame in the device shown in FIG. 1, and FIG. 3 is a communication control circuit of the device shown in FIG. FIG. 4 shows a timing chart explaining the operation of the embodiment of the present invention, and FIG. 5 shows a timing chart explaining the operation of the conventional device. In the figure, 1 is a DMA transfer control circuit, 2 is a memory, 3 is a communication control circuit, 4 is a parity error detection circuit, and 5 is an abort pattern generation circuit.

Claims (1)

[Claims] HDLC (High Level data Link)
a communication control circuit that enables communication in the control) procedure, a memory with a parity bit, and a DMA (Direct Control) that controls data transfer between the communication control circuit and the memory.
ct memory access) A communication control device equipped with a transfer control circuit, wherein the communication control circuit is provided with a circuit that generates an abort pattern in response to a parity error signal, and the parity error is sent as a write signal from the DMA transfer control circuit to the communication control circuit. A communication control device characterized in that the parity error is detected after the frame is output, and when a parity error is detected, the abort pattern is generated to invalidate the frame.