JPS6157523U - - Google Patents
Info
- Publication number
- JPS6157523U JPS6157523U JP1984142968U JP14296884U JPS6157523U JP S6157523 U JPS6157523 U JP S6157523U JP 1984142968 U JP1984142968 U JP 1984142968U JP 14296884 U JP14296884 U JP 14296884U JP S6157523 U JPS6157523 U JP S6157523U
- Authority
- JP
- Japan
- Prior art keywords
- electrical connection
- connection bumps
- flip
- semiconductor device
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Wire Bonding (AREA)
Description
第１図ａ，ｂは従来構造を示す平面図、側面図
、第２図は従来装置の実装構造図、第３図ａ，ｂ
は本考案の一実施例構造を示す平面図及び側面図
、第４図は本考案の実装構造図である。図におい
て１はシリコンチツプ、２−１〜２−４はバンプ
、３は基板、４は放熱兼用バンプである。
Figure 1 a, b is a plan view and side view showing the conventional structure, Figure 2 is a mounting structure diagram of the conventional device, Figure 3 a, b
4 is a plan view and a side view showing the structure of an embodiment of the present invention, and FIG. 4 is a diagram of the mounting structure of the present invention. In the figure, 1 is a silicon chip, 2-1 to 2-4 are bumps, 3 is a substrate, and 4 is a heat radiation bump.
Claims (1)
フリツプチツプ型半導体装置において、前記電気
接続用バンプの少くとも１つの面積を他より拡大
して形成したことを特徴とするフリツプチツプ型
半導体装置。 1. A flip-chip semiconductor device having a plurality of electrical connection bumps provided on its surface, characterized in that the area of at least one of the electrical connection bumps is formed larger than the other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984142968U JPS6157523U (en) | 1984-09-21 | 1984-09-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984142968U JPS6157523U (en) | 1984-09-21 | 1984-09-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6157523U true JPS6157523U (en) | 1986-04-17 |
Family
ID=30701281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984142968U Pending JPS6157523U (en) | 1984-09-21 | 1984-09-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6157523U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5897849A (en) * | 1981-12-07 | 1983-06-10 | Mitsubishi Electric Corp | Semiconductor element |
-
1984
- 1984-09-21 JP JP1984142968U patent/JPS6157523U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5897849A (en) * | 1981-12-07 | 1983-06-10 | Mitsubishi Electric Corp | Semiconductor element |