JPS6180465A - Generating circuit of geometric function - Google Patents

Abstract

PURPOSE:To produce a secondary function at a high speed as well as an optional secondary function by providing plural coordinate conversion circuits for primary conversion and connecting these conversion circuits to each other via a 3-state buffer. CONSTITUTION:The output of the 1st coordinate conversion circuit 10 is supplied to the 2nd coordinate conversion circuit 20 via a 3-state buffer 30. When the buffer 30 is put under an enable state by a command given from a control circuit 40, the output U of the circuit 10 is supplied to an input A of an adder 14 within the circuit 20 via the buffer 30. Here an output U is used in place of a (d) register 11 of the circuit 20 together with other (e) and (f) registers 12 and 13 used for conversion of coordinates respectively. Thus a secondary function is delivered to an output V of the circuit 20. While the 3rd coordinate conversion circuit is added to the circuits 10 and 20 for calculation of changing components of X and Y coordinates and addition of these components. Thus an optional secondary function is delivered. In other words, a secondary function can be produced at a high speed by connecting plural coordinate circuits via a 3-state buffer together with connection of a secondary function.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a geometric function generation circuit, and more specifically, to a geometric function generation circuit that can arbitrarily generate linear or quadratic functions. do.

(Prior Art) The image measurement device M is configured to, for example, image the object using an image means and measure the image of the object from the resulting image. In this type of device, a quadratic function may be generated due to the necessity of performing coordinate transformation of an image. Conventionally, quadratic functions have been created through software processing.

(Problems to be Solved by the Invention) When a quadratic function is calculated by software, the processing speed is slow, so the generation of the quadratic function is slow, and the overall image processing speed cannot be improved.

The present invention has been made in view of these points, and
The first purpose is to realize a geometric function generation circuit that can generate quadratic functions at high speed by configuring a quadratic function generation circuit with hardware.The second purpose is to create a geometric function generation circuit that can generate quadratic functions at high speed. The object of the present invention is to realize a geometric function generation circuit that can generate geometric functions.

(Means for Solving the Problems) The present invention, which solves the above-mentioned problems, firstly sets coefficients a,
A selection means for selecting one of the three types of data inputs related to b and c, a two-input adder whose one input is the output from the selection means, and an output from the adder 45 is held. A coordinate conversion circuit is provided with a register whose output becomes the other input of the adder, and is configured to output aX+bY+c from the register corresponding to the X and Y coordinates of the image scanning position via a 3-state buffer. When two sets are connected and the three-state buffer is enabled, two
The first feature is that the next function is configured so that each coordinate transformation circuit generates a linear function when the three-state buffer is disabled. One of three data inputs related to coefficients a, b, and c in response to a synchronization signal.
a two-input adder whose one input is the output from the selection means; and a register which holds the output from the adder and whose output serves as the other input of the adder Pi. Three sets of coordinate conversion circuits configured to output aX+b'/+C from the register corresponding to the X and Y coordinates of the image scanning position are prepared, and the outputs of the first and second coordinate conversion circuits are It is characterized in that it is configured to avoid generation of arbitrary quadratic functions by inputting it to the third coordinate transformation circuit.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment of the present invention. In the figure, 1o is a first coordinate conversion circuit, 30 is a 3-state buffer that receives the output of the first coordinate conversion circuit 10, and 2
0 is a second coordinate conversion circuit that receives the output of the first coordinate conversion circuit 10 via the 3-state buffer 30, and 40 is various synchronization signals (pixel clocks) from the raster scan type image processing device.

x synchronization signal, Y domei signal), the first and second coordinate conversion circuits 10. - A control circuit that controls the lh operation of the 20 and 3 state buffers 30. As the control circuit 40, for example, a microcomputer is used. Before explaining the operation of the apparatus configured in this way, the operation of the coordinate conversion circuit will first be explained. Here, the operation of the coordinate conversion circuit 10 will be explained (exactly the same applies to the coordinate conversion circuit 20).

In an image processing apparatus, in order to enlarge or reduce an image by one rotation, it is necessary to perform coordinate transformation, such as affine transformation, and read out the image memory using the transformed address. The affine transformation from the locus (Xi, Yt) to the coordinates (X2, Y2) is expressed by the following equation.

X2 = ax, +b"y', +C Y2 = dX1 +eY1 +f (1) The coordinate transformation device is used to perform the above-mentioned transformation.

In the figure, 1, 2.3 are 3-state output coefficient registers that input and hold data a, b-, and C- related to coefficients a, b, and c from a control computer, etc., and 4 are these coefficient registers. This is an adder that receives either one of 1 and 2.3 into one input. As the adder 4, a false logic operation unit (ALtJ) may be used for addition.

5 holds the output of the adder 4 and sends the output to the adder 4.
A register with a 3-state output that is applied to the other input B of the 4
0 inputs the X and Y synchronization signals and the pixel clock, which are the same signals from the raster scan type image processing device as described above, and selects the register between the coefficient registers 1, 2.3,
This is a control circuit that controls the output of the adder 4 and the register 5.

FIG. 2 is a time chart showing the operation of each part of the coordinate conversion circuit configured as described above in the case of 6 pixels in the X direction and a 4 pixel clock in the X synchronization width.

In raster scanning, pixels are scanned in the X direction in accordance with the pixel clock (c), and an X synchronization signal pulse (2) is generated when scanning one line, and a Y synchronization signal pulse (2) is generated every time one image is scanned. b) occurs.

Coefficient registers 1, 2.3 input and hold coefficients 1jla, b-, and c-, respectively, from a control computer or the like.

However, b==b-ha, c--c-ga-b', where h-x period-1, q-X synchronization width-1, and in the case of Fig. 2
lmlm=10. Xl15] Bright width=4, so h=9.
It becomes g-3.

When the Y synchronization signal is 0'', the register selection signal from the control circuit 40 selects the G register 3 for the 8 inputs of the adder 4 (Fig. 2 (d)). The output of the register 5 is (4).
Since the register enable signal shown in is 1", it is disabled (disconnected) (Fig. 2 (g)). Therefore, the B inputs of the adder 4 are all 1" (Fig. 2 (g)). e)
).

And since the carry input of adder 4 becomes "1", adder 4
The output F becomes F−C− (see FIG. 2). The value of C- is held in the register 5 (see FIG. 2).

Next, when the Y synchronization signal becomes "1" and the X synchronization signal becomes "O", the adder 4 is used from the first pixel clock (period t) in the synchronization width of the X synchronization signal to the point one clock before the last. A register 1 is selected for the 8 inputs, register 5 is output enabled, and the carry input of adder 4 is 0'.
°, and the output of the adder 4 becomes F=C-+Σa.

Next, at the time of the last clock in the synchronization width of the X synchronization signal, t is also selected for the b register 2 at the 8 inputs of the adder 4.゛The output of adder 4 is F-b-+c'+g
a=c, and the coefficient C is held in the register 5 by the clock of this resultant method.

Next, when the X synchronization signal becomes 1'', a register 1 is selected as the input of adder 4, and F=c+Σa. Output F of adder 4 is output from register 5 with a delay of one clock. .

Next, when the X synchronization signal becomes °O゛', a register 1 is selected as the 8 inputs of the adder 4, and a is sequentially added to the 8 inputs, but at the time of the last clock, register b 2 is selected as the a input.
is selected. At this time, the addition output is F=c+ha +b-
=b+c, and in the next clock, register 5 has b+c.
is retained.

The addition is repeated in the same way, and Y same +! l] signal and the X domei signal are both 1'°, that is, when actually accessing the image memory, a is added every clock, and the value obtained by adding b every line is sent from register 5. Output. That is, the output of the register 5 corresponding to the X and Y coordinates of the image scanning position is aX+bY+C.

According to the coordinate conversion circuit with the above configuration, the configuration is simple as there is only one output register, and the control and
The logic is also simple.

The operation of the coordinate transformation circuit 1o has been described above, but the situation is exactly the same for the second coordinate transformation circuit 20. Note that, like the first coordinate conversion circuit 10, the second coordinate conversion circuit 20 has registers 11, 12, 13, . It consists of an adder 14 and a register 15. The operation of the apparatus shown in FIG. 1 will be explained below for each case.

(1) Linear function mode In this mode, the three-state buffer 30 is disabled by a command from the control circuit 40.

Therefore, in this state, the first coordinate transformation circuit 10 and the second coordinate transformation circuit 2o are both independent, and can generate linear functions from their respective outputs U and V. 1
The next function generation operation is as described above.

(2) Quadratic function mode (a) X2 function mode In the pixel at coordinates (X+1.Y) to the right of the coordinates (X, Y), the square of the X coordinate is (X+1 > 2-X2 +2X+1. , a ×2 function can be generated by accumulating 2×+1 every pixel clock.

Now, the output U of the first coordinate conversion circuit 10 is U=2X+
1 generates a function. 3-state buffer 30, 1
When enabled by a command from the ill I11 circuit 40, the output U of the first coordinate conversion circuit 10 red-whites the 3-state buffer 30 and transfers it to the second coordinate conversion circuit 20.
The input signal is input to the adder 14 inside. Here, the U output is used instead of the d register 11 of the second coordinate conversion circuit 20,
If the other e register 12 and f register 13 are used for the coordinate conversion operation described above, a x2 function is outputted to the output (2) of the coordinate conversion circuit 20.

FIG. 3 is a timing chart showing the operation of each part in a simplified case where the X-direction element i=6. In the figure, 1γ1
is a Y synchronization signal, stone is an X synchronization signal, and XC is a pixel clock. FIG. 3(a) shows the operation of the second coordinate conversion circuit 20 in the x2 mode. The d register 11 is ignored and initially the e register 12 contains -i2 (--36>
However, i2 (-36) is given to the f register 13. Since the 8 inputs of the adder 14 are given the output 36 of the register 15 before the Y synchronization signal YS rises, the F output (A+8> is O) of the adder 14. The linear function (2X+1
> will be sent. Initially, it is X-O, so LI=1
becomes. At this time, the B input of the adder 14 is given the previous F output 0 via the register 15, so o1, so the current F output is A+B=1 +O-1, and F-1° U at the next pixel clock. =2X+1=3
(X=1> is sent. Register 15 is the previous F
Since the output is held, it is 1. Therefore, the F output at this time is Δ+8=3+1-4, and the same operation is repeated below F=4°. As a result, it can be seen that the output V of the register 15 is a square value of the X data.

(b) For the element at the coordinate (X+1.Y) to the right of the XY function mode coordinates (X, Y), the product of the X and Y coordinates is (X+1)Y=XY+Y. Therefore, if we accumulate Y for each pixel clock,
A Y function can be generated.

Now, the output U of the first coordinate transformation circuit 10 generates a function such that U=Y. With the three-state buffer 30 enabled, the output U of the first coordinate transformation circuit 10 enters the Δ input of the adder 14 in the second coordinate transformation circuit 20. Here, the d register 110 of the second coordinate conversion circuit 20
Use the U output instead, set the other e register 12 to O, f
If the register 13 is ignored and the coordinate conversion operation is performed, the xY function is outputted to the output (2) of the coordinate conversion circuit 20.

3b) shows the operation of the second coordinate transformation circuit 20 in the XY function mode. In the state of Y-0, V
The output is O. Next, when Y-1 is reached, the adder adds this 1 and the 8 inputs O, and the F output becomes A+8=1 +O=1, and at the next pixel clock of F-1°, the output of the adder 14 is △+B =1-1-2, and the same operation is repeated below F-2°, and the F output is output from the register 15 with a delay of one clock. As a result, it can be seen that the output of the register 15 indicates the XY value.

(c) Y2 function mode locus + 1fi (X, Y) next line locus IM (X,
Y+1>1i! In the ii element, the square of the Y coordinate is (
Y+1) 2=Y2+2Y+1. Therefore, if we accumulate 2Y+1 for each line, Y
Two functions can be generated. Now, the first coordinate conversion circuit 10 generates a function U=2Y+1, and the second coordinate conversion circuit 20 generates a coefficient e for each X opening signal Xs.
If instead of adding , the 3-state buffer 30 is enabled and U-2Y+1 is added, the Y2 function will be output to the output 2 of the register 15.

FIG. 4(9) is a diagram showing the operation of the second coordinate transformation circuit 20 in the Y2 function mode. In this mode, initially the d register 11 is 0, the e register 12 is ignored, and f
Register 13 is set to 1. V of register 15
It can be seen that the output is the value of Y2.

(d) The X2+XY mode quadratic function is not limited to the three types mentioned above, but can also generate a function that combines these.
At the pixel at coordinates (X+1°Y) to the right of (X, Y), (
Calculating the sum of X+1)2 and (X+1)・Y, we get (X+1) 2 + (X+1)・
Y=X2 +XY+2X+Y+1 Therefore, by accumulating 2X+Y+1 for each pixel clock, the X2 +XY function can be generated.

Now, the first coordinate conversion circuit 10 generates a function U-2X+Y+1, and instead of adding the coefficient d every pixel clock, the 3-state buffer 30 is enabled and tJ
By adding -2X+Y+1, the output V of the register 15 can be made into an open number X2 +XY@l. Figure 4(b) is
2. Second coordinate conversion circuit 2o in +XY control mode
FIG. In this case, d register 11 and f
Register 13 is treated as WA, and initially only e register 12 is 0.
is set to The output of register 15 is X2 +XY
It can be seen that it takes a value.

The operation of generating secondary IIl@ has been described above in detail. In the above description, an adder is used as the adder 4.14 in each coordinate conversion circuit 10.2o, but an ALLJ (logical operation unit) may also be used.

FIG. 5 is a block diagram showing another embodiment of the present invention. The device shown in the figure includes first and second coordinate conversion circuits 5
In addition to 0.60, a third coordinate conversion circuit 70 is added. That is, the first and second coordinate conversion circuits 50.
60 outputs U and ■ are respectively sent to 3-state buffers 31.
32 to six inputs of the third coordinate conversion circuit 70.

In the circuit configured in this way, the first coordinate conversion circuit 50 calculates the change in the X coordinate and adds it every pixel clock x C, and the second coordinate conversion circuit 60 calculates the change in the Y coordinate. and by adding it for each X synchronization signal XS,
Any quadratic function can be generated. An arbitrary quadratic function is output from the output W of the third coordinate transformation circuit 70.

FIG. 6 is a diagram showing the operation of the third coordinate transformation circuit 70 when generating a quadratic function of X2 +XY+Y2.

The first coordinate conversion circuit 50 outputs U=2X+Y+1, and the second coordinate conversion circuit 60 outputs V=-4Y-35.
is output. Initially the d and e registers are ignored and the f register is set to 31. It can be seen that the output W of the register takes the value x2+xY+Y2. In this way, if any quadratic function can be generated, it can be used as coordinates for correcting the geometric distortion of an image as shown in FIG.

FIG. 8 is a groove bottom view showing another embodiment of the present invention. 2
The output U of the coordinate conversion circuit 80.90.

■? Divide by J calculator 100. The output W of the divider 100 is given by the following equation.

W-U/V When performing high-speed calculations, a ROM can be used as the divider 100. According to the circuit shown in the figure, a pi-linear (bi l 1 nenr, ) function can be generated. As a result, the coordinates for correcting the barrel distortion and pincushion distortion of the image are V+ - (aX+bY+c) / (dX+eY+f) V z - (Q
X+eY+f) can be generated.

(Effects of the Invention) As described above in detail, according to the first invention, two coordinate transformation circuits that perform one-dimensional transformation are provided, and these coordinate transformation circuits are connected via a three-state buffer. , can generate a linear function or a quadratic function,
According to the second invention, any quadratic function can be generated by preparing three sets of coordinate transformation circuits. According to the present invention, since functions can be generated by hardware, high-speed processing can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the coordinate conversion circuit, and FIGS. 3 and 4 are for explaining the present invention in detail. Figure 5
The figure is a block diagram showing another embodiment of the present invention, FIG. 6 is a diagram for explaining the present invention in detail, FIG. 7 is a diagram for explaining geometric distortion correction, and FIG. 8 is a diagram for explaining geometric distortion correction. It is a figure showing an example of application of the present invention. 1~3.11~13.5.15...Register 4.14
...Adder 10.20.50.60.70.80.90...Coordinate conversion circuit

Claims (2)

[Claims] (1) A selection means for selecting one of three types of data inputs related to coefficients a, b, and c in response to a synchronization signal from a raster scan type image processing device, and an output from this selection means for one of the data inputs. a two-input adder that serves as an input; and a register that holds the output from this adder and whose output serves as the other input of the adder; Two sets of coordinate conversion circuits configured to output aX+bY+c from a register are connected via a 3-state buffer, and when the 3-state buffer is enabled, a quadratic function is generated, and when the 3-state buffer is disabled, a quadratic function is generated. , a geometric function generating circuit characterized in that each coordinate transformation circuit is configured to generate a linear function, respectively. (2) Selection means for selecting one of the three types of data inputs related to coefficients a, b, and c in response to a synchronization signal from the raster scan type image processing device, and an output from this selection means for selecting one of the data inputs. a two-input adder that serves as an input; and a register that holds the output from this adder and whose output serves as the other input of the adder; Prepare three sets of coordinate conversion circuits configured to output aX+bY+c from a register, and generate any quadratic function by using the outputs of the first and second coordinate conversion circuits as inputs to the third coordinate conversion circuit. A geometric function generating circuit characterized in that it is configured to