JPS6183047U - - Google Patents

Info

Publication number
JPS6183047U
JPS6183047U JP1984169645U JP16964584U JPS6183047U JP S6183047 U JPS6183047 U JP S6183047U JP 1984169645 U JP1984169645 U JP 1984169645U JP 16964584 U JP16964584 U JP 16964584U JP S6183047 U JPS6183047 U JP S6183047U
Authority
JP
Japan
Prior art keywords
heat sink
semiconductor element
resin material
semiconductor device
model registration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984169645U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984169645U priority Critical patent/JPS6183047U/ja
Publication of JPS6183047U publication Critical patent/JPS6183047U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/381—Auxiliary members
    • H10W72/387—Flow barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第１図は本案の一実施例を示す正断面図、第２
図は第１図の側断面図、第３図は第１図の横断面
図、第４図はリードフレームの平面図、第５図は
第４図の正面図、第６図は従来例の横断面図、第
７図は第６図の正断面図である。 図中、１は放熱板、３は吊りピン、３ａは導出
端、４は半導体素子、５はリード、６は金属細線
、７は樹脂材、７ａは樹脂モールド面である。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 放熱板に半導体素子を固定すると共に、そ
    れの電極と一端が半導体素子の近傍に位置するリ
    ードとを金属細線にて接続し、かつ放熱板、半導
    体素子の金周面を樹脂材にてモールド被覆したも
    のにおいて、上記放熱板に吊りピンを付設し、そ
    れの樹脂材からの導出端を、放熱板より離隔した
    反対側の樹脂モールド面に位置させたことを特徴
    とする半導体装置。 (2) 吊りピンを放熱板に、放熱板に形成した突
    出部によつてかしめ固定したことを特徴とする実
    用新案登録請求の範囲第１項に記載の半導体装置
    。 (3) 放熱板の裏面側にモールド被覆された樹脂
    材の厚みを薄く設定したことを特徴とする実用新
    案登録請求の範囲第１項に記載の半導体装置。
JP1984169645U 1984-11-07 1984-11-07 Pending JPS6183047U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984169645U JPS6183047U (ja) 1984-11-07 1984-11-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984169645U JPS6183047U (ja) 1984-11-07 1984-11-07

Publications (1)

Publication Number Publication Date
JPS6183047U true JPS6183047U (ja) 1986-06-02

Family

ID=30727364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984169645U Pending JPS6183047U (ja) 1984-11-07 1984-11-07

Country Status (1)

Country Link
JP (1) JPS6183047U (ja)

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