JPS6184199A - Data transfer device - Google Patents

Abstract

PURPOSE:To improve the processing capacity of a central processing unit and to shorten the processing time in general by providing a strobe signal generator circuit which operates by the decoder output of a reception circuit and generates the strobe signal to an interface circuit. CONSTITUTION:A strobe signal generator circuit 12, which operates by the decoder output of a reception circuit 1 and generates the strobe signal to an interface circuit 2, is provided between the reception circuit 1 for transmitting a decoder output relating to received data after data output and the interface circuit 2 for latching the data output of the circuit 1 and decoder output. After the circuit 1 transmits the decoder output, the circuit 2 outputs an interruption request to a central processing unit 3. Thus the unit 3 processes these outputs in the state where the data output and decoder output all appear. Accordingly it is unnecessary that software causes the unit 3 to be standby until the decoder output and data output and all appear, and therefore the processing capacity of the unit 3 can be improved by interrupting other signal processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer device suitable for transferring data such as channel selection data.

[Conventional technology]

A television receiver that allows remote channel selection and volume adjustment using a remote control transmitter has a built-in remote control receiving circuit for receiving a remote control signal sent from the remote control transmitter. The remote control receiving circuit of this stock includes a receiving circuit for receiving channel selection data, as shown in FIG. 3, for example.

As this receiving circuit 1, for example, IC name M50111P
The channel selection data received by the receiving circuit 1 is latched by the interface circuit 2 and then transmitted to the central processing unit 3. The receiving circuit 1 and the interface circuit 2 have a data bus 4 and two decode output signal lines 5,
The interface circuit 2 and the central processing unit 3 are connected by a data bus 7.

Further, the interrupt request output terminal INT of the receiving circuit 1 is connected to the interrupt request input terminal INT of the central processing unit 3 via the inverting circuit 8.

[Problem that the invention seeks to solve]

The above receiving circuit 1. In the conventional data transfer device 9 consisting of an interface circuit 2 and a central processing unit 3, the interrupt request output from the interrupt request output terminal INT of the receiving circuit 1 is as shown in FIG. The decode output, in which one of the two outputs is low level, is output almost simultaneously with the data output shown in the figure (B).
As shown in , ΔT1 (middle 12.5
μs) is output with a delay. Therefore, for data between 211 and 211, the central processing unit 3 cannot read the decoded output and cannot process the data accurately. The configuration is such that it remains in a standby state until the decoded output is supplied from the interface circuit 2. Therefore, during this standby period, the central processing unit 3 is unable to perform other signal processing, resulting in problems such as a decrease in processing ability and a prolongation of processing time.

Furthermore, in the conventional data transfer device 9, the decoded output of the receiving circuit 1 ends at ΔT2 (=25 to 37.5 μs) before the trailing edge of the data output, as shown in FIG. 2 CB). Immediately before the falling edge of the interrupt request output of receiving circuit 1,
When the central processing unit 3 accepts an interrupt, the decoded signal disappears before the decoded signal is completely read from the ink 7 process circuit 2, and accurate data processing may not be possible. There was a problem.

[Means for solving problems]

This invention solves the above problems, and includes a receiving circuit that sends out a decoded output related to received data with a delay after the data output, and a receiving circuit that transmits the data output and decoded output sent from this receiving circuit to an external device. an interface circuit that latches and outputs an interrupt request in response to a strobe signal from the interface circuit; a central processing circuit that processes latch data of the interface circuit in response to an interrupt request from this interface circuit; , and a strobe signal generation circuit that generates a strobe signal to the interface circuit. A strobe signal is supplied to the interface circuit when the data output and decode output of the receiving circuit are completed, and at that point the ink 7 process circuit outputs an interrupt request to the central processing unit.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. 1 and 2 are a circuit configuration diagram and a signal waveform diagram of each part of the circuit, respectively, showing an embodiment of the data transfer device of the present invention. Note that the same components in FIG. 1 and FIG. 3 are given the same reference numerals.

In FIG. 1, the data transfer device 11 includes a strobe signal generation circuit 12 between the decode output terminals STA, STB of the receiving circuit 1 and the strobe input terminal 8TC of the interface circuit 2,
C name: μPD8255AC-5) interrupt request output terminal INT is connected to the central processing unit [3 (I
C name: μPD780-1) interrupt request input terminal IN
It is connected to T.

The Stroop signal generation circuit 12 receives the two decode outputs of the receiving circuit 1 as input, and includes a Nant gate circuit 12a that outputs a high-level signal during the decode output period, and a capacitor/resistor type that differentiates the output of the Nant gate circuit 12a. a differentiating circuit 12b, and a diode clamp circuit 1 that outputs a positive polarity pulse out of the output of the differentiating circuit 12b.
2C and the output of the diode clamp circuit 12c, and the output terminal 8T of the interface circuit 2 is connected to the strobe input terminal 8T of the interface circuit 2.
It consists of an inverting circuit 12d, etc., which supplies the signal to C.

Inverting circuits 14 and 15°16 are connected to the read command output terminal RD, write command output terminal WR, and input/output request terminal l0RQ of the central processing unit 3, respectively, and the outputs of the respective inverting circuits 14 and 15 are connected to Nant gate circuits 17 and 18, which receive the output of the inversion circuit 16, are connected to the read command input terminal RD and write command input terminal WR of the interface circuit 2, respectively.

Now, the receiving circuit 1 receives the channel selection data, and as shown in Fig. 2 (5)
Assume that a time ΔT□ has elapsed after the start of data output shown in FIG. In this case, the data input terminal D4. of the interface circuit 2. While the decode output is supplied to D5, the decode output is also supplied to the strobe signal generation circuit 12.

After one decoded output of the receiving circuit 1 becomes low level, the Stroop signal generating circuit 12 generates a differential circuit 12b.
Until the time ΔT corresponding to the differential time constant of
A strobe signal shown in FIG. 2 (Q) is supplied to the strobe input terminal STC of the interface circuit 2.

The interface circuit 2 latches the data and its decoded signal supplied from the receiving circuit 1 at the rising edge of the strobe signal, sends out the interrupt request output shown in FIG. 8 to the interrupt request input terminal INT of the central processing unit 3.

The central processing unit 3, which has accepted the interrupt request from the interface circuit 2, sends the read command output shown in FIG. 2 to the read command input terminal RD of the interface circuit 2.
supply to. As a result, during the output period of the read command, the latch data of the interface circuit 2 (data output and decode output from the receiving circuit 1) is
is the data input terminal of the central processing unit 3. to D7, and signal processing is performed.

In this way, the data transfer device 11 is configured so that an interrupt request for data processing is output to the central processing unit 3 when the data output and decode output of the receiving circuit 1 are completed, so that the data transfer device 11 can be decoded by software. There is no need to provide a standby period for output, and the period required for signal processing by the central processing unit 3 can be suppressed to the necessary minimum.

Further, since the central processing unit 3 does not perform signal processing during the output period difference ΔT1 or ΔT2 between the decode output and the data output of the receiving circuit 1, accurate and reliable signal transfer is always possible.

〔Effect of the invention〕

As explained above, according to the present invention, there is a connection between a receiving circuit that sends out a decoded output related to received data with a delay from the data output, and an interface circuit that latches the data output and decoded output of this receiving circuit. Since a strobe signal generation circuit is provided which is activated by the decoded output of the receiving circuit and generates a strobe signal to the interface circuit, the interface circuit outputs an interrupt request to the central processing unit after the receiving circuit sends out the decoded output. , this allows the central processing unit to process the data output and decoded output when these outputs are present, so the software puts the central processing unit in a standby state until the decoded output and data output are fully present. There is no need to maintain the signal, and by interrupting other signal processing, excellent effects such as increasing the processing capacity of the central processing unit and shortening the overall processing time can be achieved.

[Brief explanation of the drawing]

1 and 2 are circuit configuration diagrams and signal waveform diagrams of various parts of the circuit, respectively, showing an embodiment of the data transfer device of the present invention, and FIGS. 3 and 4 are circuit configuration diagrams, respectively, showing an example of a conventional data transfer device. FIG. 2 is a diagram and a signal waveform diagram of each part of the circuit. 1...Reception circuit, 2...Interface circuit, 3.
...Central processing unit, 11...Data transfer device, 12.
・・Stroop signal generation circuit.

Claims (1)

[Claims] A receiving circuit that sends out a decoded output related to received data with a delay from the data output, and a receiving circuit that latches the data output and decoded output sent from this receiving circuit using a strobe signal from the outside and outputs an interrupt request. an interface circuit, a central processing circuit that processes latch data of the interface circuit in response to an interrupt request from the interface circuit, and a strobe signal generator that operates according to the decoded output of the receiving circuit and generates a strobe signal to the interface circuit. A data transfer device consisting of a circuit.