JPH03957B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer device suitable for transferring data such as channel selection data.

[Conventional technology]

Television receivers that allow remote channel selection and volume adjustment using a remote control transmitter have a built-in remote control receiving circuit for receiving remote control signals sent from the remote control transmitter. This type of remote control receiving circuit has a receiving circuit 1 for receiving channel selection data, as shown in FIG. 3, for example.
As this receiving circuit 1, for example, IC name is M50111P.
The channel selection data received by the receiving circuit 1 is latched by the interface circuit 2 and then transmitted to the central processing unit 3. Receiving circuit 1
and the interface circuit 2 are connected to the data bus 4 by two decode output signal lines 5 and 6, and the interface circuit 2 and the central processing unit 3
are connected by a data bus 7.

Also, the interrupt request output terminal of receiving circuit 1
INT is connected to an interrupt request input terminal of the central processing unit 3 via an inversion circuit 8.

[Problem that the invention seeks to solve]

A conventional data transfer device 9 consisting of the above-mentioned receiving circuit 1, interface circuit 2 and central processing unit 3
As shown in FIG. 4C, the interrupt request output from the interrupt request output terminal INT of the receiving circuit 1 is
While it is output almost simultaneously with the data output shown in A of the same figure, the decode output in which either one of them becomes low level at the time of output is ΔT ₁ (≒12.5 μs) from the interrupt request output as shown in B of the same figure. Output is delayed. Also, this decode output is the D of channel selection data.
4. Compatible with D5. Therefore, regarding the data between ΔT ₁ , the central processing unit 3 cannot read the decoded output and cannot process the data accurately. 3 is configured to remain in a standby state for a period of ΔT ₁ until it is supplied with channel selection data from the interface circuit 2. Therefore, during this standby period, the central processing unit 3 had problems such as a decrease in processing capacity and a prolongation of processing time.

Further, in the conventional data transfer device 9, the decoded output of the receiving circuit 1 is shortened to ΔT ₂ (≒25 to 37.5 μs) before the trailing edge of the data output, as shown in FIG. 2B.
Therefore, if the central processing unit 3 accepts an interrupt just before the falling edge of the interrupt request output of the receiving circuit 1, the decoded signal will disappear before it is completely read from the interface circuit 2, and the decoded signal will not be accurate. There were problems such as the inability to process data in some cases.

[Means for solving problems]

This invention solves the above problems, and includes a receiving circuit that sends out a decoded output related to received data with a delay after the data output, and a receiving circuit that transmits the data output and decoded output sent from this receiving circuit to an external device. an interface circuit that latches and outputs an interrupt request in response to a strobe signal from the interface circuit; a central processing circuit that processes the latch data of the interface circuit in response to the interrupt request from this interface circuit; and a central processing circuit that operates based on the decoded output of the receiving circuit. , and a strobe signal generation circuit that generates a strobe signal to the interface circuit.

[Effect]

This invention provides an interface circuit that controls the transmission and reception of signals between a receiving circuit and a central processing unit.
A strobe signal is supplied when the data output and decode output of the receiving circuit are completed, and at that time the interface circuit outputs an interrupt request to the central processing unit.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. 1 and 2 are a circuit configuration diagram and a signal waveform diagram of each part of the circuit, respectively, showing an embodiment of the data transfer device of the present invention. Note that the same components in FIG. 1 and FIG. 3 are given the same reference numerals.

In FIG. 1, a data transfer device 11 is a receiving circuit 1.
between the decode output terminal of , and the strobe input terminal of interface circuit 2,
In addition to providing a strobe signal generation circuit 12,
Interface circuit 2 (IC name: μPD8255AC-
5) interrupt request output terminal INT is connected to the central processing unit 3 (IC name: μPD788-) via the inversion circuit 8.
1) is connected to the interrupt request input terminal.

The strobe signal generation circuit 12 receives the two decoded outputs of the receiving circuit 1 as input, and includes a NAND gate circuit 12a that outputs a high-level signal during the decoded output period, and a capacitor/resistance type differentiator that differentiates the output of the NAND gate circuit 12a. circuit 12b
, a diode clamp circuit 12c that outputs only positive polarity pulses from the output of the differentiating circuit 12b, and an inversion circuit 12d that inverts the polarity of the output of the diode clamp circuit 12c and supplies it to the strobe input terminal of the interface circuit 2. .

Note that the read command output terminal of the central processing unit 3
Inverting circuits 14, 15,
16 are connected, and Nanand gate circuits 17 and 18 whose inputs are the outputs of the inverting circuits 14 and 15 and the output of the inverting circuit 16 are connected to the read command input terminal and the write command input terminal of the interface circuit 2, respectively. There is.

Now, the receiving circuit 1 receives the channel selection data, and the second
After the start of data output shown in Figure A, time ΔT ₁ has elapsed, and one of the decoded outputs is as shown in Figure B.
Suppose it becomes low level. In this case, while the decode output is supplied to the data input terminals D ₄ and D ₅ of the interface circuit 2, the decode output is also supplied to the strobe signal generation circuit 12.

After one decoding output of the receiving circuit 1 becomes low level, the strobe signal generating circuit 12 generates a signal.
Time ΔT corresponding to the differentiation time constant of the differentiation circuit 12b
The strobe signal shown in FIG. 2C is supplied to the strobe input terminal of the interface circuit 2 until the period of time elapses.

The interface circuit 2 latches the data supplied from the receiving circuit 1 and its decoded signal at the rising edge of the strobe signal, sends out the interrupt request output shown in FIG. 2D from the interrupt request output terminal INT, and outputs the interrupt request output shown in FIG. This is supplied to the interrupt request input terminal of the central processing unit 3 via.

The central processing unit 3 that has received the interrupt request from the interface circuit 2 supplies the read command output shown in FIG. 2E to the read command input terminal of the interface circuit 2. As a result, during the output period of the read command, the latch data of the interface circuit 2 (reception circuit 1
data output and decoded output) are supplied to data input terminals D ₀ to D ₇ of the central processing unit 3,
Signal processing is performed.

In this way, the data transfer device 11 is configured so that an interrupt request is output to the central processing unit 3 for data processing when the data output and decoded output of the receiving circuit 1 are received. There is no need to provide a waiting period after an interrupt request is made by the software, and the period required for signal processing by the central processing unit 3 can be suppressed to the necessary minimum.

Further, since the central processing unit 3 does not perform signal processing during the output period difference ΔT ₁ or ΔT ₂ between the decode output and the data output of the receiving circuit 1, accurate and reliable signal transfer is always possible.

〔Effect of the invention〕

As explained above, according to the present invention, there is a connection between a receiving circuit that sends out a decoded output related to received data with a delay from the data output, and an interface circuit that latches the data output and decoded output of this receiving circuit. Since we provided a strobe signal generation circuit that is activated by the decoded output of the receiving circuit and generates a strobe signal to the interface circuit, the interface circuit sends an interrupt request to the central processing unit after the receiving circuit sends out the decoded output. This allows the central processing unit to process the data output and the decoded output when they are present, and therefore the central processing unit can There is no need to keep the device in a standby state, and excellent effects such as increasing the processing capacity of the central processing unit and shortening the overall processing time can be achieved.

[Brief explanation of the drawing]

1 and 2 are circuit configuration diagrams and signal waveform diagrams of various parts of the circuit, respectively, showing an embodiment of the data transfer device of the present invention, and FIGS. 3 and 4 are circuit configuration diagrams, respectively, showing an example of a conventional data transfer device. FIG. 2 is a diagram and a signal waveform diagram of each part of the circuit. 1...Reception circuit, 2...Interface circuit, 3...
Central processing unit, 11... data transfer device, 12... strobe signal generation circuit.

Claims (1)

[Claims] 1 A receiving circuit that sends out decoded output regarding received data with a delay from the data output, latches the data output and decoded output sent from this receiving circuit using an external strobe signal, and outputs an interrupt request. a central processing circuit that processes latch data of the interface circuit in response to an interrupt request from the interface circuit; and a central processing circuit that operates based on the decoded output of the receiving circuit and generates a strobe signal to the interface circuit. A data transfer device consisting of a strobe signal generation circuit.