JPS62199032A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Semiconductor devices that use GaAs as a semi-insulating compound semiconductor substrate and form transistors in an epitaxial layer on the substrate are attracting attention for their high speed and are being developed. The present invention describes the structure and manufacturing method of an integrated circuit that facilitates the formation of an element isolation layer necessary for integrating this type of semiconductor device and improves performance.

[Industrial application field]

The present invention relates to an integrated circuit using a compound semiconductor, and in particular to a structure of an element isolation layer and a method for manufacturing the same.

GaAs or AlGa on a semi-insulating GaAs substrate
Techniques for forming FETs or heterobipolar transistors (HBTs) by epitaxially growing As layers are being developed.

Conventionally, development has progressed mainly as a transistor with a single structure, but in order to take advantage of its high speed as an integrated circuit, there is a demand for a brainer structure and an improvement in element isolation methods.

[Conventional technology]

An example of the structure and manufacturing method of an integrated circuit using a compound semiconductor according to conventional technology will be briefly described.

FIG. 3 is a partial sectional view of a semiconductor device in which a conventional HBT, which has a large current amplification factor and is characterized by high speed, is integrated.

The transistor structure is made of GaAsJi except for the emitter, and only the emitter is laminated with AlGaAs having wide bandgap characteristics.

In FIG. 3, on a GaAs semi-insulating substrate 1, n”
-GaAs collector contact layer 2 is 1.0 μm, n
--GaAs collector layer 3 is 1. OpmSp”-GaA
s base layer 4 is 0.1 #m, n-AlGaAs emitter N5 is 0.3 μm, n”-GaAs contact layer 6
are sequentially laminated with a thickness of 0.2 μm.

A U-shaped or V-shaped device isolation groove 7 is etched into the substrate on which the epitaxial layer is grown by anisotropic dry etching.
The trench is then filled with an insulating material 8 by vapor phase growth. As an insulating material, Si 2 N 4 or Si
Oz is used.

FIG. 3 shows an example in which high resistance regions 9 are provided by implanting oxygen ions on both sides of the device isolation groove in order to reinforce the device isolation function.

Using the substrate with the above element isolation structure, the collector,
By opening each contact hole in the base and forming an emitter electrode E, a collector electrode C, a base electrode B, and a wiring layer connecting these, an integrated circuit having an HBT structure is completed.

[Problem that the invention seeks to solve]

In the method of forming an element isolation groove according to the conventional technique described above, it is necessary to form a deep groove of 2 to 3 μm that reaches the semi-insulating substrate 1.

It is difficult to fill this separation trench with an insulating material in the second step, so the filling step is divided into two steps as shown in Figure 3.
First, a portion 8 is filled, and the insulating material outside the isolation trench region is removed and planarized.

Next, the 8° portion is buried again to flatten the isolation trench.

In addition to having to perform the process twice, there are other problems such as the formation of cavities inside the eight-edge material during the embedding process, which deteriorates the quality.

[Means for solving problems]

The above-mentioned problems are solved by the structure of a semiconductor integrated circuit and its manufacturing method of the present invention, which uses a semi-insulating bulk crystal substrate as a substrate and an isolation layer on its side.

That is, the structure is such that a plurality of recessed buried regions surrounded by an element isolation layer are formed in a semi-insulating compound semiconductor substrate, and a semiconductor layer is buried in the buried regions by epitaxial growth. .

The functional element has a structure formed in the semiconductor layer.

In addition, the manufacturing method includes selectively forming an insulating film on the upper surface of an element isolation layer of a semi-insulating compound semiconductor substrate, and using the insulating film as a mask, a plurality of recess-shaped buried regions are formed in the substrate by etching. form.

Next, a semiconductor layer is buried in the buried region by epitaxial growth, and the insulating film and the stacked layers thereon are removed.

Next, functional elements are formed on the semiconductor layer to complete an integrated circuit.

[Effect]

In the present invention, instead of opening a narrow device isolation trench in a substrate and burying the groove in the conventional method, a buried region with a wide opening is opened by etching, and a semiconductor layer is epitaxially grown in this wide opening. The structure and manufacturing method is that it is embedded.

Therefore, the embedding process is easy and the steps are simplified, contributing to the production of highly reliable integrated circuits.

〔Example〕

Fig. 1 is a cross-sectional view of the structure of an integrated circuit manufactured by the method of the present invention, and Figs. 2 (a) to (Q) are cross-sectional views showing the manufacturing method mainly consisting of the formation of an insulating separation layer in the order of steps. .

In FIG. 2(a), a photoresist film 10 is laminated on the entire surface of a GaAs semi-insulating substrate 1, and an opening is formed in the upper surface 11 of the element isolation layer by patterning using a lithography method.

FIG. 2 (in BL, a SiO film is laminated on the entire surface by the CVD method, and an S*Oz film 1 is formed on the upper surface 11 of the separation layer.
2, the resist film in other areas and the Si on it
O! The membrane is removed by lift-off.

In FIG. 2C, a buried region 14 surrounded by an element isolation layer 13 is formed using a sulfuric acid-based wet etching solution as a mask for the Si peritoneum 12.

In FIG. 2(d), by the MBE method, the n"-GaAs collector contact layer 2 is deposited with a thickness of 1.0 am, the n--GaAs collector layer 3 is deposited with a thickness of 1-OtlrnSp", and the GaAs base layer 4 is deposited with a thickness of 0.1/jm, n- ALGaAs emitter 1!5
0.3pmSn”-GaAs contact rri60
．． An epitaxial layer is sequentially grown in the buried region 14 to a thickness of 2 μm.

At this time, polycrystalline GaAs, A
A product jii15 made of lGaAs grows. Product 111
5 along with the 5in2 film using a hydrofluoric acid etching solution. This state is shown in FIG. 2(e).

Subsequent emitter electrode E1 base electrode B, collector electrode C
The formation of , and the formation of wiring layers are the same as the conventional methods. As a result, the integrated circuit shown in the cross section of FIG. 1 is completed.

〔Effect of the invention〕

As explained above, the integrated circuit structure and manufacturing method of the present invention makes it extremely easy to form an element isolation layer, which greatly contributes to reducing the number of steps and improving quality.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the structure of a semiconductor integrated circuit according to the present invention, FIG. A structural cross-sectional view of a semiconductor integrated circuit according to the present invention is shown. In the drawing, 1 is a GaAs semi-insulating substrate, 2 is an n"-GaAs collector contact layer, and 3 is an n-
-GaAs collector layer, 4 is p"-GaAs base layer, 5 is n-AlGaAs emitter layer, 6 is n"-GaAs contact layer, 7 is element isolation trench, 8.8' is insulating material, 9 is high resistance region , 10 is a photoresist film, 11 is the upper surface of the element isolation layer, 12 is a Sin film, 13 is the element isolation layer, 14 is a buried region, 15 is a laminated layer, E is an emitter electrode, B is a base electrode, C is a collector The electrodes are shown respectively. Figure 81 M2FIJ @ 2 Figure 113 Figure

Claims (2)

[Claims] (1) A semi-insulating compound semiconductor substrate (1) with an element isolation layer (
13) surrounded by a plurality of concave-shaped embedded regions (1
4) is formed, semiconductor layers (2) to (6) are stacked in the buried region,
A semiconductor integrated circuit characterized in that a functional element is formed in the semiconductor layer. (2) Element isolation layer of semi-insulating compound semiconductor substrate (1) (
13) A step of selectively forming an insulating film (12) on the upper surface (11), and a step of forming a plurality of concave-shaped buried regions (14) in the substrate by etching using the insulating film as a mask. a step of epitaxially growing and embedding semiconductor layers (2) to (6) in the embedding region; and forming a functional element in the semiconductor layer after removing the insulating film and the laminated layer (15) thereon. 1. A method for manufacturing a semiconductor integrated circuit, comprising the steps of: