JPS6232552U - - Google Patents
Info
- Publication number
- JPS6232552U JPS6232552U JP1985123064U JP12306485U JPS6232552U JP S6232552 U JPS6232552 U JP S6232552U JP 1985123064 U JP1985123064 U JP 1985123064U JP 12306485 U JP12306485 U JP 12306485U JP S6232552 U JPS6232552 U JP S6232552U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- utility
- device characterized
- model registration
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例を示す縦断面図、第
２図は本考案の他の実施例を示す縦断面図、第３
図は半導体装置の従来例を示す縦断面図、第４図
は第３図のＡ―Ａ′線断面図である。 Ｐ……パツケージ、１，１′……下部チツプキ
ヤリア、２，２′……上部チツプキヤリア、１ａ
，２ａ……窪部、３，４……ワイヤボンデイング
パツド、５，５′，６，６′……ＩＣチツプ、７
，８……リードワイヤ。
２図は本考案の他の実施例を示す縦断面図、第３
図は半導体装置の従来例を示す縦断面図、第４図
は第３図のＡ―Ａ′線断面図である。 Ｐ……パツケージ、１，１′……下部チツプキ
ヤリア、２，２′……上部チツプキヤリア、１ａ
，２ａ……窪部、３，４……ワイヤボンデイング
パツド、５，５′，６，６′……ＩＣチツプ、７
，８……リードワイヤ。
Claims (1)
- 【実用新案登録請求の範囲】 (1) 複数のＩＣチツプを、同一パツケージの対
向しあう内壁面に互いに向かい合わせて実装して
なることを特徴とする半導体装置。 (2) 実用新案登録請求の範囲第１項において、
前記パツケージは中央内壁部に窪部を有する上下
一対のチツプキヤリアからなり、該窪部に前記Ｉ
Ｃチツプを前記各チツプキヤリアの内周縁に設け
たワイヤボンデイングパツドに接続しつつ実装し
てなることを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985123064U JPS6232552U (ja) | 1985-08-09 | 1985-08-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985123064U JPS6232552U (ja) | 1985-08-09 | 1985-08-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6232552U true JPS6232552U (ja) | 1987-02-26 |
Family
ID=31013825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985123064U Pending JPS6232552U (ja) | 1985-08-09 | 1985-08-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6232552U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04324670A (ja) * | 1991-03-30 | 1992-11-13 | Samsung Electron Co Ltd | 半導体パッケージ及びその製造方法 |
-
1985
- 1985-08-09 JP JP1985123064U patent/JPS6232552U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04324670A (ja) * | 1991-03-30 | 1992-11-13 | Samsung Electron Co Ltd | 半導体パッケージ及びその製造方法 |