JPS623376A - Document picture processor - Google Patents

Abstract

PURPOSE:To increase the document picture processing speed by using the picture buses of two systems which can be actuated independently of each other. CONSTITUTION:Information is transferred among a picture buffer memory 5, a display memory 6 and each processing circuit by means of picture buses I and II of two systems which can be actuated independently of each other. The bus I contains an address bus 18 for a picture buffer memory 5, a data bus 22 connected with the memory 5 and a vertical/horizontal converting circuit 10, a data bus 24 connected with a magnification/reduction circuit 11, a graphic processing circuit 12, a scanner/printer interface 15 and a compression/expansion circuit 16 and control buses 19 and 25 respectively. While the bus II contains a data bus 23 connected with a display memory 6 and the circuit 10, an address bus 20 for the memory 6, a data bus 26 connected with the circuit 11 and the circuit 12 and control buses 21 and 27 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a document image processing device that electronically performs input, output, display, editing, etc. of document images.

[Technical background of the invention and its problems]

As typified by facsimiles and electronic files,
Document image processing devices that electronically process document images are being actively developed. The purpose of developing these devices is to improve work efficiency by digitizing conventional paper-based general work, especially office work, and to make it easier to handle complex work as work becomes more sophisticated. It's about doing. These devices perform information processing such as scanning a document image with a scanner, converting it into an electrical signal, compressing it and transmitting it, or storing it in an image memory, processing it, and outputting it to an image printer. will be held.

In such a document image processing apparatus, in order for a user to operate it arbitrarily to truly improve work and improve work efficiency, the following points must be fully considered. First, it is easy and flexible to transfer document image information between the various means that make up the system. If transfer between certain means is not possible, or if it is possible but requires many steps, the scope for improvement will be limited. The second is that the processing speed is high.

In this type of device, the operability of the device as well as the functions it can process are important factors that determine the performance of the device. Among these, processing speed is one of the decisive points for the device's man-machine interface, and unless it satisfies the φ level or higher, work efficiency may be reduced.

However, in conventional document image processing devices, these two points are not necessarily satisfied.

For example, information can be transferred flexibly between each means but the transfer speed is extremely slow, or high-speed information transfer is possible but the transfer destination is limited, or flexible transfer can be performed relatively quickly. However, the hardware mechanism and procedures up to the start of transfer were usually extremely complex. This does not allow for sufficient improvement in work efficiency.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and it provides a document image that extremely facilitates the simultaneous transfer of document/document image information between multiple means constituting a system, and also improves system throughput and speeds up processing. The purpose is to provide processing equipment.

[The fear of invention]

The present invention provides at least an image buffer memory for temporarily storing document image information, a display memory for displaying document images, an input/output means for document image information, an image bus used for transferring document image information, and management of these. In a document image processing apparatus having a control device for controlling the image bus, two image buses capable of operating independently as image buses are provided, and connections between the image buffer 7 memory and the display memory and the two image buses are provided. In addition to providing an image bus switching control circuit to control, an active input operating mechanism that is selectively connected to the image bus and takes in image information by its own control signal, and a passive input that takes in image information by a control signal from another. operating mechanism,
The present invention is characterized in that it is provided with an information mediating means having an active output operation mechanism that sends out image information in response to a control signal issued by itself, and a passive output operation mechanism that sends out image information in response to a control signal from another.

〔Effect of the invention〕

Since the document image processing apparatus according to the present invention has two image buses that can operate independently, it is possible to access the image buffer memory and the display memory simultaneously, thereby improving the throughput of the system. In addition, by connecting circuits that perform scaling, image reversal, etc. to two image buses, advanced documents such as writing image information from a scanner to image buffer 1 memory and writing a reduced image to display memory at the same time can be used. Image processing becomes possible. In addition, the uniform information transfer mediating means provided between both image buses enables extremely high-speed, advanced and flexible image processing, including pipeline-like processing that transfers information from one image bus to the other. can be executed.

(Example of the invention) The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic block diagram of a document image processing system according to an embodiment. 1 is an information processing unit (hereinafter referred to as CPU) that is a device that manages and controls this device, 2 is a CPLJ program memory that stores a program that describes this control procedure, and 3 is CPU 1 and other input/output devices such as a CRT terminal. It is an interface for connecting etc. This document image processing device uses the control signal from CPtJl as C
The information is supplied via the PU bus 4 to a memory that stores document image information and to a document image processing means to execute desired processing.

5 is an image buffer memory for temporarily storing document image information;
6 is a display memory that temporarily stores document image information to be displayed, and 7 and 8 are two-dimensional address generation circuits that generate addresses for accessing two-dimensional rectangular areas in these memories. Reference numeral 9 denotes a display controller that takes in data from the display memory 6 according to the display cycle and controls the data to be displayed on the display. 10 is a vertical/horizontal conversion circuit that rotates the orientation of the document image every 90 degrees; 11 is a document image enlargement/reduction circuit; and 12 is a graphic processing circuit that generates a character pattern and draws it in the display memory 6 and image buffer memory 5. be. 13 and 14 are scanners and printers that are input/output means for document images; 15;
is a scanner-printer interface having a function of importing document image information read by the scanner 13 and a function of importing document image information stored in the memories 5 and 6 and sending it to the printer 15.

16 demodulates and decompresses compressed document image information transferred from an external communication control AM device and imports it, or stores it in memory 5.6.
This is a compression/expansion circuit that compresses and modulates document image information and sends it to the outside.

In order to transfer information between the image buffer memory 5 and display memory 6 and each processing circuit, the present invention provides two systems of image buses (1) and (2) that can operate independently. Here, the image bus ■ includes an address bus 18 for the image buffer memory 5, a data bus 22 to which the image buffer memory 5 and the vertical/horizontal conversion circuit 10 are connected, an enlargement/reduction circuit 119, a graphic processing circuit 12, a scanner/printer interface 15, and a compression circuit. It collectively refers to the data bus 24 to which the decompression circuit 16 is connected, and the control bus 19.25, and the image bus 2 is the address bus 20.25 for the display memory 6. A data bus 2 to which a display memory 6 and an aspect conversion circuit 10 are connected.
3. It collectively refers to the data bus 26 to which the enlargement/reduction circuit 11 and the graphic processing circuit 12 are connected, and the control buses 21 and 27. In this embodiment, the image buffer memory 5
is connected to only one data bus 22, and the display memory 6
is connected only to the other data bus 23.

Therefore, the data bus 22 on the image buffer memory 5 side and the data bus 24 to which the scaling circuit 112, figure processing circuit 12, etc. are connected are divided, and the data bus 20 on the display memory 6 side and the scaling circuit 11° figure The data bus 26 to which the processing circuit 12 and the like are connected is divided, and the connection therebetween is controlled by the image bus switching control circuit 17.

Some processing operations performed by the document image processing apparatus configured as described above will be described below.

(1) When transferring data between the scanner 13 or printer 14 and the image buffer memory 5, the image bus switching control circuit 17 connects the data buses 22 and 24 and the control buses 19 and 25. 2
Data transfer is performed via 4. During this time, if it is desired to output graphic data or the like to the display memory 6, this is done via the data buses 23 and 26.

(2) When the data in the image buffer 1 memory 5 is rotated and printed out, the data bus 22 and the aspect conversion circuit 10 are connected, and the data from the image buffer memory 5 is transferred to the aspect conversion circuit 10. After entering and being rotated, for example, 90', the bus switching side - 〇.
・2゛:1 1・′□ Output to 14. During this time, data bus 23 and
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(3) Input from scanner 3 into image buffer
・'□・While writing to this memory 5, reduce and rotate at the same time
7.

,・ When writing to the display memory 6, the data
, ＼ The data flowing through the screen 24 is taken in by the enlargement/reduction circuit 11.
,・.

;(:: The image is reduced while viewing and outputted to the data bus 26. The vertical/horizontal conversion circuit 10 is connected to the data bus 23.
ゞ′；・；： Here, the reduced image data is rotated 90 degrees and displayed.
゛、・”.

The data is written to the display memory 6.
, IJ゛(4) Scanner 3 and printer on the Gappo Bus■
]・J・- 14 and image buffer 7 memory 5.
:.

ξ While sending, enlarge or reduce character patterns etc.
. . . When writing to the memory 6, the character pattern in the graphic processing circuit 12 is once taken into the enlargement/reduction circuit 11 via the data bus 26 by the clock from the enlargement/reduction circuit 11. After the enlargement/reduction process, the data is again written to the display memory 6 via the data buses 26 and 23. In this case, image data is partially transferred on the image bus (2) in synchronization with the read clock and write clock of the enlargement/reduction circuit 11.

(5) When the data in the image buffer memory 5 is enlarged or reduced and written to the display memory 6, the data in the image buffer memory 5 is sent to the enlargement/reduction circuit 1 via the data buses 22 and 24.
1, and its output data is transferred to data bus 26.2.
3 to the display memory 6. In this case, read data runs on the image bus (2), write data runs on the image bus (2), and high-speed data transfer is performed by the pipeline operation of the enlargement/reduction circuit 11.

Furthermore, the image is converted into a bus via an aspect/horizontal conversion circuit 10.

If the data is connected between 2 and 3, advanced data processing such as rotating and scaling the data will be performed at extremely high speed.

(6) By connecting the data buses 24 and 23, data transfer between the display memory 6 and the scanner 13 or printer 14 is possible.

In the image information processing operation described above, in order to perform flexible and high-speed processing using the two image buses and the data transfer between (2), this "image path (2)" is required.

■The mediating means for transferring image information between the two plays an important role.

That is, this information transfer mediating means is capable of flexible and sophisticated information processing by providing an active operating mechanism and a passive operating mechanism in the information importing section and the transmitting section, respectively. In this embodiment, the information mediating means having such a function is integrated into the enlarging/reducing circuit 11.

Figure 2 shows an enlargement/reduction circuit 1 equipped with such information mediating means.
This is an example of configuration 1. In the figure, 31 is an enlargement/reduction calculation mechanism, 32 is an input data latch circuit, and 33 is an output data latch circuit. The data acquisition section includes an active input operating mechanism 34 and a passive input operating mechanism 35, and 36 is a selector for a latch signal of input data outputted from these.

Similarly, the data sending section includes an active output operation mechanism 37 and a passive output operation mechanism 38, and 39 is a selector for the end signal of the data output sequence outputted from these. Reference numeral 40 denotes a control circuit that performs sequence control using these input/output operating mechanisms.

41 to 50 indicate human output buffers. Although not shown in the figure, input data, output data, and control signals such as transfer lock can be selectively connected to image bus (2) and image bus (2).

In the image information capture section, during active operation, the active input operating mechanism 34 outputs a data read control signal PRDC, and input data is captured in response to the response signal QPACK, and during passive operation, an external data write control signal PW is output.
The passive operating mechanism 35 is moved by the TC to take in input data. This image information? i (A specific example of the configuration of the import section is shown in FIG. 3. The active input operating mechanism 34 generates the data read control signal PRDC)
It is composed of a C generator 341 and an AND gate 342. The passive input operating mechanism 35 is constituted by an AND gate 351. When the input request signal from the sequence control circuit 40 is not output, the AND gate 351 is in a prohibited state, and even if it receives the data write control signal PWTC, it does not return the response signal PACK and makes the external means stand by. It has become.

In the image information sending section, during active operation, the active output operation mechanism 37 outputs the data write control signal PWTC to send out data, and a response signal PACK is sent to the active output operation mechanism 37 to send data.
The sequence is such that the sending operation ends at . During passive operation, the passive output operation mechanism 38 receives an external data read control signal PRDC and ends the data sending operation. FIG. 4 shows a specific example of the configuration of this image information sending section. The active output operating device 1i37 is composed of a PWTC generator 371 that generates a data write control signal PWTC and an AND gate 372. The passive output operating mechanism 35 is composed of an AND gate 351.

Enlargement/reduction circuit 1 equipped with image information mediating means as described above
1, a specific operational example of the mediating transfer of image information between the image buses I and II will be described below.

The specific bus configuration in this embodiment is as shown in FIG. 5, for example. Address buses 18 and 19 for accessing the image buffer memory 5 and display memory 6 are AD-
There are 26 A2S buses and 16 Do-DIS data buses 22, 23, 24, and 26. Control signal bus 1
9, 21° 25.27 is a data read control signal PRDC as a clock for image information transfer, a data write control signal @P W T C1, and a response signal P for these.
In addition to the ACK signal, there are six signals for control signals such as a horizontal line end signal HEND and a vertical direction end signal VEND, and a selection signal ADSEL for two sets of address generation circuits 7 and 8.

First, the operation of displaying a document image stored in the image buffer memory 5 on the display will be described. In the case of this image processing operation, the image buffer memory 5 is connected to the image bus ■, and the display memory 6 is connected to the image bus ■, so the data importing section side of the enlarging/reducing circuit 11 is connected to the image bus ■, and the data sending section side is connected to the image bus ■. Connection relationships are selected such that they are respectively connected to image bus ■. First, the enlargement/reduction circuit 11 having an image information mediating means has an active input operation mechanism 34 at an image information take-in section and a send-out section, respectively.
, is activated to activate the active output operating mechanism 37. The enlargement/reduction circuit 11 starts operating 1.

! image buffer containing document image information.
.

, t A data read control signal PRDC is output from the active input operating mechanism 34 to the memory 5. image :
・”゛,゛One of the two sets of address generation circuits 7.8 is assigned to the address generation circuit that accesses the buffer memory 5, and the address generation circuits access the buffer memory 5 in sequence according to the data read control signal J!PRDC from the enlargement/reduction circuit 11. Address is updated.Response signal PACK to data read control signal PRDC
is returned from the image buffer memory 5 onto the PACK line and expanded.

In the reduction circuit 11, its active input operation mechanism 34 is
, j is received, the image information from the image buffer 7 memory 5 is taken into the input data latch 32. The image information captured in this way is subjected to predetermined enlargement or reduction processing by the enlargement/reduction calculation mechanism 31.

The enlarged or reduced image information is sent out by the data write control signal PWTC output from the active output mechanism 37 of the same enlargement/reduction circuit 11 to the display memory 6. In this case as well, one of the address generation circuits 7.8 is assigned to access the display memory 6, and the addresses are sequentially updated in accordance with the data write control signal PWTC. A response signal PACK to this data write control signal PWTC is outputted from the display memory 6 onto the PACK line and taken in by the active output mechanism 37 of the enlargement/reduction circuit 11. As a result, the enlarging/reducing circuit 11 moves to the next sequence.

The timing of the above image information transfer is as shown in FIG.

Next, document image information is taken in from an external device via the image input/output means, written to the display memory 6, and displayed.

A case will be explained below. The compression/expansion circuit 16 will be taken as an example of image input means.

When displaying document image information imported from an external device, the compression/decompression circuit 16 is an active operating means.
It operates as a server and sends the transfer control signal itself and displays it.
However, especially in the case of display, the size at which the document image is displayed is limited due to the various displays that interact with the system.
, 1. There are many cases where it is desired to display the image in a reduced size. The conventional method for responding to this request is to
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. 1' Large reduction processing is performed. According to this method, the display can be flexibly enlarged and reduced.
□ is possible, but the scaling process is limited to display.
; For example, you can enlarge or reduce a part of the document image information stored in the image buffer memory and copy it to another part.
You will not be able to perform processes such as viewing, zooming, or scaling the document image stored in the image buffer memory and displaying it on the left side.

In this embodiment, there are two image buses I and II, and the enlargement/reduction circuit 11 is provided with the transfer mediating means as described above, so that document image information taken in from the outside can be directly transferred to the display memory 6 or the image data. The data can be written into the buffer memory 5, or can be enlarged or reduced through the enlarging/reducing circuit 11 before being written. In the former case,
The captured information is directly displayed in the display memory 6 by the data line 1 to control signal PWTC output from the compression/expansion circuit 16.
At this time, the image information is transferred from the data bus 24 via the image bus switching control circuit 17 and then via the data bus 23. In the latter case, the passive input operation mechanism 35 of the enlarging/reducing circuit 11 is operated, and the enlarging/reducing circuit 1 is operated according to the data write control signal PWTC from the compression/expansion circuit 16.
Import image information in step 1, perform enlargement or reduction processing,
This time, the active output operation of the enlargement/reduction circuit 11 Fj9. Structure 37
Writing to the display memory 6 is performed by a data write control signal PWTC output from the display memory 6. That is, the image information taken in by the compression/expansion circuit 16 at this time is transferred to the data bus 2.
4, passes through the enlargement/reduction circuit 11, enters the data bus 26, is sent to the data bus 23 via the image bus switching circuit 17, and is written into the display memory 6.

As described above, according to this embodiment, extremely flexible image processing is possible in terms of image information transfer between the image buffer memory 5 and display memory 6, writing of image information from outside the T into the display memory 6, etc. . Moreover, as is clear from FIGS. 2 to 4, there are two image buses 1. The image information transfer mediating means between I and I is realized by extremely simple hardware.

By the way, as seen in the previous explanation, it is often necessary to perform scaling processing on document image information imported from an image input/output means before displaying it. For example, it may be necessary to perform some processing such as copying a portion or overlaying another image.Alternatively, it may be necessary to successively change the reduction ratio of the same document image in order to set it to the state that is most easily viewed by the user. In this case, it is necessary to store the displayed document image in the image buffer 7 memory and read it out as necessary for display or image editing processing. Conventionally, for this processing, , two phases are required: first, document image information is stored in the image buffer memory, and then it is displayed, and therefore a sufficient processing speed cannot be obtained.

In the present invention, as already mentioned, two image buses ■ and ■ are provided, and these can operate independently.
The means for sending document images can simultaneously transfer images to a plurality of other means.

In the above operation example, 1. The document image information sent from the image input/output means is an image (the image can be transferred to the image buffer memory and the display memory at the same time. A problem with simultaneous transfer is the difference in the capture speed of multiple capture sides.The present invention solves this problem by arranging that the respective response signals to the transfer lock are ANDed on the image bus. This can be solved by

FIG. 7 is a diagram for explaining such an embodiment. In the figure, 61 is the control signal)
line, 621.622.

623 respectively send a response signal P to this PACK line 61.
This is a PACK output stage of each means that outputs ACK. Each output stage is comprised of an oven collector gate 63 and its movable control gate 64, and becomes movable when the enable signal EN is high.

With such a configuration, the response signal PAC issued by the plurality of means
The PACK line 61 does not go high while any one of Ks to PACKa is low, and PAC is not activated until the outputs of all PACK output stages 621 to 623 become high.
K line 61 becomes high. This makes it possible to maintain complete synchronization of image information transfer, allowing simultaneous transfer to multiple means.

Note that, instead of adopting the configuration of calculating logical product using a gate circuit as shown in FIG. 7, it is also possible to adopt a method in which, for example, only the response signal PACK of the means with the slowest response is returned to the PACK line. .

This is also substantially the same as performing logical AND on the same bus, and the same effect can be obtained.

Next, the configuration and operation of the memory access control circuit portion in the device of the present invention will be explained in more detail.

As shown in FIG. 1, this device uses two two-dimensional address generation circuits 7 in order to simultaneously control access to the image buffer memory 5 and the display memory 6.
and 8 are provided between the two image buses ■ and ■.

Considering only the image information transfer between the image buffer memory 5 and the display memory 6 and the information transfer between these memories and other means, the two-dimensional address generation circuits 7 and 8 have one for the image buffer memory 5 and the other for the image buffer memory 5. is for display memory 6,
Although they may be fixedly connected to different image buses (2) or (2), in the embodiment shown in FIG. 1, both two-dimensional address generation circuits 7, 8 are connected to the image bus (2).

■It can be connected to any of the following. This is to ensure that image information is transferred only within the image buffer memory 5 and only within the display memory 6, and the image information is transferred only within the display memory 6.

When transferring image information as described above, the image bus switching control circuit 17, enlargement/reduction circuit 11, graphic processing circuit 12, scanner/printer interface 15, compression/expansion circuit 16, etc. are used to load and read image information. Control clock and image information only to the image bus ■or■
It is only necessary to input and output data to and from the image buffer memory 5 and the display memory 6, and there is no need to control access to the image buffer memory 5 and display memory 6.

FIG. 8 shows a schematic configuration of the two-dimensional address generation circuits 7 and 8. 71 connects this address generation circuit to the CPU
1, and is a CPU interface for connecting to 72
are registers 73x and 74x selected by CPU 1 and set with command CMD necessary for access control.
, 75x, 73Y, 74y, 75y are the same <CPU1
This is a register in which the star 1 to address X5TA, YSTA regarding X and Y coordinates, the number of steps X5TP, YSTP which is the minimum unit for calculating the address, and the number of repetitions XN, YN of address calculation are set.

Counters 76X, 76Y, timing control circuit 77, multiplexer 78x.

78Y, adders 79x and 79y are parts for calculating the X and Y addresses. Multiplexer 78x.

Address data obtained from 78Y is interface 8
It is designed to be output to address bus 18 or 20 via 0X and 80Y. 81x.

Reference numeral 81Y is an interface for controlling the timing of outputting or stopping address data, which is taken into this address generation circuit by a control signal sent from another device via the control buses 19, 21.

In a device in which two two-dimensional address generation circuits 7 and 8 are connected between image buses I and II, the most basic method, for example, is to extract an image from a certain area in one document and paste it into another area. The operation when performing editing processing will be explained next.

In FIG. 9, the area to be extracted within the document at this time is shown by a solid line, and the transfer destination rRli'! is shown by a broken line, and the address relationship of each area is shown. When performing such image editing, for example, one two-dimensional address generation circuit 7 accesses the transfer source area, and the other two-dimensional address generation circuit 8 accesses the transfer destination area, selected by CPtJl, and access control is performed. The necessary commands, the start address for the X and Y coordinates, the number of steps, the number of repetitions, etc. are set in each register to enable access control. Next, for example, when the data read control signal PRDC is output from the image bus switching control circuit 17 to the control bus 19 on the image bus side, the two-dimensional address generation circuit 7 selected as the transfer source starts operating. , calculates a predetermined address and outputs it to the address bus 18 on the image bus side. As a result, the image buffer 7 memory 5 connected to the image bus side is accessed, and the image information in the transfer source area is read out and output to the data bus 22.

Image bus switching 11511 When the I11 circuit 17 finishes taking in the transfer source image information from the data bus 22, it then transfers the data write control signal PWC and the previously read image information to the control bus 19 and data bus 22, respectively. Output. When the data write control signal PWTC is output to the control bus 19, the two-dimensional address generation circuit 7 stops outputting the transfer source address and address data, and transfers the data to the other two-dimensional address generation circuit 8 selected as the transfer destination. starts working. The two-dimensional address generation circuit 8 generates a transfer destination address and outputs it to the address bus 18, thereby writing image information into the transfer destination area of the image buffer memory 5. When this writing process is completed, the image bus switching control circuit 17 outputs a data read control signal PRDC to the control bus 19 in order to read the next image information from the transfer source again.
Read processing is performed in the same manner as described above. At this time, the two-dimensional address generation circuit 8 stops outputting the transfer destination address, and the two-dimensional address generation circuit 7 calculates and outputs the next address.

By sequentially repeating the above read/write process over the entire predetermined fA area, image dislike information transfer within one sentence as shown in FIG. 9 is carried out two-dimensionally and at high speed. At this time, address generation in each address generation circuit 7°8 is as follows:
A predetermined area is scanned two-dimensionally according to the flowchart shown in FIG. That is, the ninth
In the case of image transfer as shown in the figure, a command from the CPU 1 sends the start address (SX port, SY port), (DXa port), along with the commands necessary for each address generation circuit.
, DYo ), number of steps in X direction 5XSTP, DXS
TP, Y-direction step 7a SYSTP, DYSTP, X-direction repetition number M, Y-direction repetition number N, etc. are set, and the main scanning direction is set as the X direction, and access is made by sequentially adding the number of steps in both the X and Y directions. is executed. During this time, the image bus switching control circuit 17 only inputs and outputs image information and read and write control signals, and image transfer within the image@1<rough memory 5 is performed.

FIGS. 11(a) to 11(q) show that image transfer can be performed in various ways by selecting the direction in which the two two-dimensional address generation circuits 7.8 generate the transfer source and transfer destination addresses. In the image transfer shown in FIG. 9, both of the two address generation circuits use the main scanning direction as the X direction, and generate addresses by sequentially adding steps.
). In addition, as shown in the flowchart in Figure 10, select the main scanning direction as either the X direction or the Y direction, and add the number of steps to the start address to generate the address in the X direction and the address in the Y direction. By specifying whether to go forward or down, image editing such as 90° rotation, 180° rotation, horizontal reversal, vertical reversal, arbitrary angle rotation, etc., as illustrated in FIG. 11, becomes possible.

Furthermore, in the example of image transfer described above, it is possible to perform in-line scaling processing simply by changing the number of steps set in the two-dimensional address generation circuit for the transfer source and the two-dimensional address generation circuit for the transfer destination.

In other words, if the number of steps at the source and destination is the same, an image of the same size will be transferred, but if the number of steps at the destination is set to 1/'2 of the source, the image m at the destination will be the same as the source. The image is 1/
2 will be reduced. In this case, there is no need to use the scaling function of the scaling circuit 11 shown in FIG.

Similar to image transfer within image buffer memory 5
'Image transfer within the display memory 6 is also possible. this
In this case, the access control by the address generation circuits 7 and 8 is performed using the address bus 2o and the control bus 21 on the image bus ■ side, and the image information is also transferred via the data bus 23 on the image bus ■ side. be done.

Furthermore, the transfer of image information between the image buffer memory 5 and the display memory 6 mentioned above, for example, the scanner, 13
When the image is written to the image buffer memory 5 from
゛At the same time, the character pattern from the graphic processing circuit 12
,,゛.

The information is stored in the display memory 6 and displayed on the display.
,.

Image processing such as image processing is also easily possible through access control by the two two-dimensional address generation circuits 7 and 8. In these image processes as well, the image bus switching control circuit 17, scanner/printer, etc.

The interface 15, graphic processing circuit 12, etc.
- Storing image information two-dimensionally in a predetermined area of each memory by simply transferring read and write control signals and image information to the necessary bus without being equally aware of access control to the memory. I can do it. Since the two two-dimensional address generation circuits 7.8 can each operate independently, they do not affect each other, and the direction and unit of address generation can be set independently. For example, scanner 13
When inputting an image to the image buffer memory 5 in units of 16 bits, the number of steps of the two-dimensional address generation circuit 7 selected for the image buffer 7 memory 5 side is set to 16, and on the other hand, inputting the image from the graphic processing circuit 12 to the display memory When writing image information in units of 8 bits to 6, the number of steps of the two-dimensional address generation circuit 8 selected on the display memory 6 side may be set to 8.

Also, the screen size (height and width of the area) in the customer's memory.
may also be different.

By providing the two two-dimensional address generation circuits 7 and 8 between the two image buses and (1) as described above, it is necessary to provide access control means for each of the various means for transferring information to the image buffer memory and display memory. disappears. Furthermore, as mentioned above, since the two address generation circuits 7 and 8 are configured as exactly the same hardware, the scale of the control program and hardware can be reduced, and the development period can also be shortened. Further, by simply changing the commands and parameters for each of the two-dimensional address generation circuits 7 and 8, it is possible to perform various types of access control and perform various image editing processes, as described above.

By the way, in Figure 8, the addresses of the output X and Y coordinates are output as they are as two-dimensional addresses, but in reality, the X addresses corresponding to the X and Y coordinates of the two-dimensional area of the image are output. and Y address are given to the memory as a one-dimensional address as a lower address and an upper address of the memory, respectively. For example, as shown in Figure 112(a), 2”
The memory space of 4096 dots usually constitutes a one-dimensionally continuous memory space in units of 8 bits (or 16 bits, etc.) as shown in FIG. 12(1)). In this case, if the address is a bit address, A22 to An
(80 is the LSB side) is the X address, A22 to A11 (A
22 is the MSB side) as the Y address and A22 to An are given to the memory. In such a memory space, for example, 1728 dots l-x as shown by diagonal lines in FIG.
When an image of 2,400 dots (for example, equivalent to an A4 size image of 8 dots/#) is stored in memory, the first
As shown by diagonal lines in FIG. 2(d), a portion of the continuous memory space is occupied in a discrete manner, resulting in poor memory usage efficiency.

In addition, when editing images of various sizes, it is necessary to develop editing programs that directly handle physical addresses that depend on the implemented memory configuration.

It is inconvenient to improve, and flexible management of document images is difficult.

The present invention performs address control that solves these problems.

FIG. 13 shows an embodiment of an address generation circuit that solves this problem and allows the memory space expressed by -dimensional addresses to correspond to various image sizes so that it can always be used efficiently.

This configuration differs from the basic configuration shown in FIG. 8 by providing an XW register 83 set by the CPUI for weighting the Y address in accordance with the image size. An address conversion circuit 82 is provided for generating continuous one-dimensional addresses using the output of the address converter 82.

FIG. 14 shows a specific configuration example of this address conversion circuit 82. The multiplier 821 multiplies (XW)X (Y) by [lXW set in the XW register 83 and the Y address from the multiplexer 78y. The adder 822 adds the □: multiplication result of the multiplier 821 and the X address of the multiplexer 78x, calculates A=(XW)X(Y)+(X), and converts the two-dimensional address into a one-dimensional address. are doing. If the output A of this adder 822 is directly output to the address bus 18 or 20, then the output A will be output as is.

The logical address of the memory becomes the physical address as is.
,・.

The address is given to the image buffer memory 5 or display memory 6 as a one-dimensional address. The above-mentioned XW value is arbitrarily set depending on the image size during editing, so
According to the above formula, image information of an arbitrary size area can be continuously stored in a one-dimensional memory space. That is, the first
It is possible to eliminate wasteful memory areas as shown in FIGS. 2(C) and 2(d). Furthermore, by performing address conversion on the output A of the adder 822 using the conversion table 823, images of various sizes can be managed flexibly.

A specific example of image management using this address conversion will be described next. For example, as shown in FIG. 15, three types of component images A, B, and C of different sizes are stored in an image buffer memory 5, and their physical addresses, logical addresses, component numbers, etc. are managed. The part with number 1 has physical address OOOO
It is stored in a continuous area from OH to 0IFFFH (hexadecimal number), and the part with number 2 has physical address 020000H.
It is stored in a continuous area from ~037FFFH,
The part with number 2 is logically at the logical address 000oOH-
It is managed as being stored in 017FF''FH. The same applies to the part with number 3. Let us now consider the case where part number 2, picture 1IIB, is deleted and part picture 11D is registered. Part number 2, physical address L/S020000H-037F of image buffer memory 5
The area below FF)l and 070000H becomes a free area. However, since the physical addresses necessary for registering a new part image are not consecutive, it has not been possible to register this using the deleted address area of part image B in the past. In the present invention, the conversion table 82 shown in FIG.
By rewriting the contents of 3, discrete areas can be treated as if they were continuous areas. That is, in this case, the conversion table 823 is converted from the physical address 038000o-06FFFFo to 0500 by the CPU 1.
00o-087FFFo, 070000o-087F
Change FFH to 038000H-04FFFFH. As a result, as shown in FIG. 16, a continuous address area can be secured for the component image, and component image information with component number 4 is newly added.

By rewriting the contents of the conversion table 823 in this way, parts and literature of various sizes can be managed and handled consistently, and the self-made buffer memory 5 and display memory 6 can be used effectively. In addition, conversion between logical addresses and physical addresses can be done flexibly, and complex parts management, memory management, etc. can be processed using logical addresses in the management program, and development efficiency and reliability of the management program can be improved.

FIG. 17 shows a schematic configuration of the conversion table 823 of the address conversion circuit 82 as described above. The RAM 8231 is a core memory of the conversion table 823 and stores conversion data. write data port 8232,
Fj input address port 8233 and read address ports 1-8234 are each three-state ports,
Turns on only when reading or reading conversion data. When writing conversion data, the CPU interface 71 enables the write address port 823q, sets the write address of the RAM 8231, and writes the write data from the write data port 8232.

At the initial stage, conversion data is written so that the read address from the adder 822 is outputted from the RAM 8231 without being passed through. For example, if the read address from the adder 822 is 0OOOH-07FFH, the conversion data is written so that the output of the RAM 8231 is also 0000M-07FFH. Next, as shown in FIG. 16, when handling various parts, the contents of the RAM 8231 are rearranged to output the necessary physical addresses as described above in accordance with the management of each part. For example, if A11-Al1 of address An''-A2S is left unchanged and A1s to A2S can be mapped through the conversion table 823, the physical address 038000H of part number 3 in FIG. To set the address to 050000H,
Conversion table 823 RAM 8231 (7) 7 address 0
007H to 000Ao k-1! Just change it. If other data are sequentially rewritten in the same way, the 16th
It is mapped to a physical address as shown in the figure.

In the concrete prototype example of the present inventors, the X address,
The Y address and
= 64 Mbits, i.e., can handle images up to AO at 8 dots/m), and furthermore, the upper 1
One bit is converted from a logical address to a physical address using a conversion table 823. This makes it possible to map addresses in units of 4 to 4 bytes (1 byte = 8 bits), and in the case of 8 dots/'re, 22.6 IN
It has become possible to logically handle images of various sizes using an 11-sided image as a unit, and to flexibly occupy and release memory areas of various sizes, divide into two, and include two.

The address conversion circuit 82 is not limited to that shown in FIG. For example, the entire address conversion circuit 82 is stored in RAM or RO.
It can be configured with a memory such as M. In this case, the value of address conversion according to various image sizes is
Calculate the above formula in U1 etc. and store the value in RAM or R.
Write it to OM and use multiplexer 78x, 78y
Address conversion is performed with reference to the X address, Y address, and set value XW of the XW register 83, and the results are provided to the interfaces 80X and 80Y. Further, the multiplier 821 in the address conversion circuit 82 may also be a multiplier-dedicated LSI, or may be configured by combining adders.

FIG. 18 shows the operation 70- of the address conversion circuit 82 when the function of the multiplier 821 is realized using an adder. In this case, when the Y address is ±1, ±xw
After adding up and performing the multiplication process of (XW) x (Y),
The addition of (XW)X (Y)+(X) is performed. Furthermore, the conversion table 823 can be written at any time, during or before or after operation. Naturally, the units to be converted using the conversion table 823 are appropriately set depending on the performance, specifications, purpose, etc. of the device.

The invention is not limited to the embodiments described above. For example, as shown in FIG. 19, the scanner/printer interface 15 and the compression/expansion circuit 16 may also be connected to the image bus (2).

With this configuration, the enlargement/reduction circuit 111, the graphic processing circuit 12. Scanner/printer interface 15. The compression/decompression circuits 16 are all connected to two image buses (■ and ■), and each can access the buffer memory 59 and the display memory 6 on both sides using a free bus, increasing the flexibility of the entire system. The performance and speed will further increase.

Furthermore, the two two-dimensional address generation circuits 7 and 8 are integrated into one module, and internally have two systems of memory (image buffer memory and display memory, or transfer source and transfer destination in one memory). Access control may also be performed. In this case, one two-dimensional light generation circuit 71 may be configured to output addresses for the image buffer memory 51 and the display memory 6 in a time-division manner. Also, when transferring images between memories, the transfer source and transfer destination addresses are
;-) In the same way, output to each memory in time division. 1.7"゛.

Bye. As a method for this time division, it is sufficient to provide two systems of output stages and latches from the address conversion circuit 82, and output enable the latched address at each output time and output it to the address bus. This makes the device even smaller and cheaper. Conversely, the two-dimensional address generation circuit may be configured with three or more modules to increase speed and flexibility.
・−.

In addition, the image buffer memory 5 and display memory 6
.

Not LC memory, but magnetic disk or optical disk
”, the address generated from the two-dimensional address generation circuit 7.8 is composed of information such as track number, sector number, disk number, etc. In this case, the above-mentioned Memory access control can be performed in the same manner as in the embodiment.The same applies when using further memory such as a magnetic bubble memory or a hologram memory.

Furthermore, by operating one of the two-dimensional address generation circuits 7.8 in combination with the image bus switching control circuit 10, simple graphic processing such as straight lines, diagonal lines, and filling in rectangular areas can be performed quickly and easily. can. For example, data “FO” (hexadecimal number) is set in the image bus switching control circuit 10, and the image bus switching control circuit 10
FO" data and a data write control signal are output to the data bus 22 and control bus 19, respectively, and the two-dimensional address generation circuit 8 sequentially outputs addresses to the address bus 20. Then, the display memory 6 has a line width of 4. Bit straight lines can be drawn.

When data of °'80'' is set in the image bus switching control circuit 10, a straight line with a line width of 1 bit can be drawn.Furthermore, when data of °'FF' is set, a specified area can be drawn. It can be filled with white or black.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the overall configuration of an embodiment of a document image processing device according to the present invention, FIG. 2 is a diagram showing the configuration of its enlargement/reduction circuit, and FIG. 3 is a diagram showing an image 3 in the enlargement/reduction circuit. FIG. 4 is a diagram showing an example of the configuration of the step capture section, FIG. 4 is a diagram showing an example of the configuration of the image information sending section, FIG. 5 is a diagram showing an example of the bus configuration with the configuration of FIG. 1, and FIG. FIG. 7 is a diagram showing a configuration example of a response signal sending unit in response to control signals from other sources using a plurality of means; FIG. 8 is a diagram showing an example of the basic configuration of a two-dimensional address generation circuit; Fig. 9 is a diagram for explaining the operation of image transfer, Fig. 10 is a diagram showing the flow of address generation in the address generation circuit, and Fig. 11 (
a) to (Q) are diagrams showing various access control examples for image editing, FIGS. 12(a) to (d) are diagrams for explaining the operation of normal one-dimensional address generation, and FIG. FIG. 14 is a diagram showing a configuration example of a specific two-dimensional address generation circuit in an embodiment of the present invention, FIG. 14 is a diagram showing a configuration example of the address conversion circuit section, and FIGS. 17 is a diagram illustrating an example of the configuration of the conversion table of FIG. 14; FIG. 18 is a diagram illustrating the flow of one-dimensional address generation in the address conversion circuit;
FIG. 9 is a diagram showing the configuration of a document image processing apparatus according to another embodiment. 1... CPU, 2... CPU memory, 3... Interface, 4... CPU bus, 5... Image buffer memory, 6... Display memory, 7, 8... Two-dimensional address Generation circuit, 10... Vertical/horizontal conversion circuit, 11...
Enlargement/reduction circuit (including information transfer mediating means), 12... Graphic processing circuit, 13... Scanner, 14... Printer, 15... Scanner/printer interface, 16
. . . Compression/expansion circuit, 17 . . . Image bus switching control circuit, 18° 20 . . . Address bus, 22.23, 24.
26...Data bus, 19, 21, 25.27...
controller] to roll bus, 34...active input operation mechanism, 3
5... Passive input operation mechanism, 37... Active output operation R
structure, 38... Passive output operation mechanism, 82... Address conversion circuit, 823... Conversion table. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 3 Figure 4 Figure 7 Figure 9 Figure 11 Forwarding source Forwarding nine frauds M nine (a) (C) ) phase.

Claims (3)

[Claims] (1) An image buffer memory that temporarily stores document image information, a display memory that temporarily stores document image information to be displayed,
In a document image processing apparatus that includes an input/output means for document image information, an image bus used for transferring document image information, and a control device for managing and controlling these, two systems of images that can operate independently as the image bus are provided. an image bus switching control circuit that is selectively connected to the image bus and that controls the document image processing by controlling the control signal output from the image bus; an active input operating mechanism that captures information; a passive input operating mechanism that captures document image information based on control signals from others;
A document characterized in that it is equipped with an information transfer mediating means having an active output operation mechanism that sends out document image information in response to a control signal issued by itself, and a passive output operation mechanism that sends out document image information in response to a control signal from another. Image processing device. (2) The document image processing apparatus according to claim 1, wherein the information transfer mediating means is integrated with a mechanism for enlarging/reducing document image information. (3) The response signals output by the image buffer memory, display memory, and other means in response to control signals from other means are logically ANDed and sent to the image bus. document image processing device.