JPS623377A - Document picture processor - Google Patents

Abstract

PURPOSE:To increase the document picture processing speed by using picture buses of two systems which can be actuated independently of each other and giving access simultaneously to both a picture buffer memory and a display memory. CONSTITUTION:Information is transferred among a picture buffer memory 5, a display memory 6 and each processing circuit via picture buses I and II of two systems which can be actuated independently of each other. The memories 5 and 6 are connected to the data buses 22 and 23 respectively. Then the part between the bus 22 and a data bus 24 connected with a magnification/ reduction circuit 11, a graphic processing circuit 12, etc. is divided. At the same time, the part between a data bus 20 at the side of the memory 6 and a data bus 26 connected with the circuit 11, the circuit 12, etc. is also divided. Then the connection among these divided parts are controlled by a picture bus switch control circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a document image processing apparatus that electronically performs input, output, display, collection of Ii, etc. of document images.

[Technical background of the invention and its problems]

As typified by facsimiles and electronic files,
Document image processing devices that electronically process document images are being actively developed. The purpose of developing these devices is to improve work efficiency by digitizing conventional paper-based general work, especially office work, and to make it easier to handle complex work as work becomes more sophisticated. It's about doing. These devices perform information processing such as scanning a document image with a scanner, converting it into an electrical signal, compressing it and transmitting it, or storing it in an image memory, processing it, and outputting it to an image printer. will be held.

In such a document image processing apparatus, in order for a user to operate it arbitrarily to truly improve work and improve work efficiency, the following points must be fully considered. First, it is easy and flexible to transfer document image information between the various means that make up the system. If transfer between certain means is not possible, or if it is possible but requires many steps, the scope for improvement will be limited. The second is that the processing speed is high.

In this type of device, the operability of the device as well as the functions it can process are important factors that determine the performance of the device. Among these, processing speed is one of the decisive points for the device's man-machine interface, and unless it satisfies a certain level or higher, work efficiency may be adversely reduced.

However, in conventional document image processing devices, these two points are not necessarily satisfied.

For example, information can be transferred flexibly between each means but the transfer speed is extremely slow, or high-speed information transfer is possible but the transfer destination is limited, or flexible transfer can be performed relatively quickly. However, the hardware mechanism and procedures required to start the transfer were often quite lengthy. This does not allow for sufficient improvement in work efficiency.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and is a document image processing system that greatly facilitates the simultaneous transfer of document image information between multiple means constituting a system, and that improves system throughput and speeds up processing. The purpose is to provide 8 processing options.

[Summary of the invention]

The present invention provides at least an image buffer memory for temporarily storing document image information, a display memory for displaying document images, an input/output means for document image information, an image bus used for transferring document image information, and management of these. In a document image processing device having a control device for controlling the image bus, two image buses capable of operating independently as image buses are provided, and connections between the image buffer memory and the display memory and the two image buses are controlled. The image bus switching control circuit is characterized in that it is provided with an image bus switching control circuit.

〔Effect of the invention〕

Since the document image processing apparatus according to the present invention has two image buses that can operate independently, it is possible to access the image buffer memory and the display memory simultaneously, thereby improving the throughput of the system. In addition, by connecting circuits that perform scaling, image reversal, etc. to two image buses, advanced documents such as writing image information from a scanner to the image buffer memory and writing reduced image data to the display memory at the same time can be used. Image processing becomes possible. Furthermore, an image processing device connected to both image buses can perform pipeline-like processing to transfer information from one image bus to the image bus being used, making extremely high-speed image processing possible.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic block diagram of a document image processing apparatus according to an embodiment. 1 is an information processing unit (hereinafter referred to as CPU) that is a device that manages and controls this device; 2 is a CPU program memory that stores a program that describes this control procedure;
3 is an interface for connecting the CPU 1 with other input/output devices such as a CRT terminal. Main text - The image processing device uses this control signal from CPU1 as CPLJ.
The information is supplied to a memory for storing document image information and a document image processing means via the bus 4, and desired processing is executed.

5 is an image buffer memory for temporarily storing document image information;
Reference numeral 6 is a display memory that temporarily stores text image information to be displayed, and reference numerals 7 and 8 are two-dimensional address generation circuits that generate addresses for accessing two-dimensional rectangular areas in these memories. Reference numeral 9 denotes a display controller that takes in data from the display memory 6 according to the display cycle and controls the data to be displayed on the display. 10 is a vertical/horizontal conversion circuit that rotates the orientation of a document image every 90°; 11 is a document image enlargement/reduction circuit; 12 is a graphic processing circuit that generates a character pattern and draws it in the display memory 6 and image buffer memory 5. It is. 13 and 14 are scanners and printers that are input/output means for document images;
Reference numeral 5 denotes a scanner-printer interface which has a function of capturing document image information read by the scanner 13 into the internal memory and a function of capturing document image information stored in the memory 5.6 and sending it to the printer 15.

16 demodulates and decompresses compressed document image information transferred from an external communication control device and imports it, or memory 5.6
This is a compression/expansion circuit that compresses and modulates text image information and sends it to the outside.

In order to transfer information between the above image buffer memory 5 and display memory 6 and each processing circuit, the present invention provides two systems of image buses and (2) that can operate independently. Here, the image bus ■ includes an address bus 18 for the image buffer memory 5, a data bus 22 to which the image buffer memory 5 and the vertical/horizontal conversion circuit 10 are connected, an enlargement/reduction circuit 119, a graphic processing circuit 12, a scanner/printer interface 15, and a compression circuit. It collectively refers to the data bus 24 to which the decompression circuit 16 is connected, and the control bus 19.25, and the image bus (■) is the address bus 20 for the display memory 6, to which the display memory 6 and the vertical/horizontal conversion circuit 10 are connected. data bus 2
3. It collectively refers to the data bus 26 to which the enlargement/reduction circuit 11 and the graphic processing circuit 12 are connected, and the control buses 21 and 27. In this embodiment, image buffer 1 memory 5
is connected to only one data bus 22, and the display memory 6
is connected only to the other data bus 23.

Therefore, the data bus 22 on the image buffer memory 5 side and the data bus 24 to which the scaling circuit 112, graphic processing circuit 12, etc. are connected are divided, and the data bus 20 on the display memory 6 side and the scaling circuit 11° graphic processing The data bus 26 to which the circuit 12 and the like are connected is divided, and the connection between them is controlled by the image bus switching control circuit 17.

Some processing operations performed by the document image processing apparatus configured as described above will be described below.

(1) When transferring data between the scanner 13 or printer 14 and the image panzer memory 5, the image bus switching control circuit 17 connects the data buses 22 and 24 and the control buses 19 and 25, and 2
Data transfer is performed via 4. During this time, if it is desired to output graphic data or the like to the display memory 6, this is done via the data buses 23 and 26.

(2) When the data in the image buffer memory 5 is rotated and printed out, the data bus 22 and the aspect conversion circuit 10 are connected, and the data from the image buffer memory 5 enters the aspect conversion circuit 10 and is converted into a 90 After being rotated, it is output to the printer 14 via the data bus 24 via the bus switching control circuit 17. During this time, access to the display memory 6 via the data buses 23 and 26 is possible.

(3) When writing the input from the scanner 13 to the image panzer memory 5 while simultaneously reducing the size and rotating it before writing it to the display memory 6, the data flowing through the data bus 24 is reduced while being taken in by the enlargement/reduction circuit 11. and output to the data bus 26. The vertical/horizontal conversion circuit 10 is connected to the data bus 23
The reduced image data is rotated by 906 and written into the display memory 6.

(4) When image data is being transferred between the scanner 13 or printer 14 and the image buffer memory 5 on the image bus ■, when character patterns, etc. are enlarged or reduced and written to the display memory 6, the clock from the enlargement/reduction circuit 11 is used. The character pattern in the graphic processing circuit 12 is once taken into the enlarging/reducing circuit 11 via the data bus 26. After the enlargement/reduction process, the data is again written to the display memory 6 via the data buses 26 and 23. In this case, on the image bus (2), the transfer of image data is controlled in synchronization with the read clock and write clock of the enlargement/reduction circuit 11.

(5) When the data in the image buffer memory 5 is enlarged or reduced and written to the display memory 6, the data in the image buffer memory 5 is sent to the enlargement/reduction circuit 1 via the data buses 22 and 24.
1, and its output data is transferred to data bus 26.2.
3 to the display memory 6. In this case, read data runs on the image bus (2), write data runs on the image bus (2), and high-speed data transfer is performed by the pipeline operation of the enlargement/reduction circuit 11.

Furthermore, the image is converted into a bus via an aspect/horizontal conversion circuit 10.

If the data is connected between 2 and 3, advanced data processing such as rotating and scaling the data will be executed at high speed.

(6) By connecting the data buses 24 and 23, data transfer between the display memory 6 and the scanner 13 or printer 14 is possible.

In the image information processing operation described above, in order to perform flexible and high-speed processing using the two systems of image path and the data transfer between (1) and (2), this image bus I is required.

■The mediating means for transferring image information between the two plays an important role.

That is, this information transfer mediating means is capable of flexible and sophisticated information processing by providing an active operating mechanism and a passive operating mechanism in the information importing section and the transmitting section, respectively. In this embodiment, the information mediating means having such a function is integrated into the enlarging/reducing circuit 11.

Figure 2 shows an enlargement/reduction circuit 1 equipped with such information mediating means.
This is an example of configuration 1. In the figure, 31 is an enlarged/reduced representation 1l
11 mechanism, 32 is an input data latch circuit, and 33 is an output data latch circuit. The data acquisition section includes an active input operation mechanism 34 and a passive input operation mechanism 35.
6 is a selector for a latch signal of input data outputted from these.

The data sending section similarly includes an active output operating mechanism 37 and a passive output operating mechanism 38, and 39 is a selector for the end signal of the monitor output sequence outputted from these. A control circuit 40 performs sequence control using these input/output operation mechanisms.

41 to 50 indicate human output buffers. Although not shown in the figure, input data, output data, and control signals such as transfer lock can be selectively connected to the image bus or the image bus.

In the image information capture section, during active operation, the active input operation mechanism 34 outputs a data read control signal PRDC, and input data is captured in response to the response signal PACK, and during passive operation, an external data write control signal PW is output.
The passive operating mechanism 35 is operated by the TC to take in input data. FIG. 3 shows a specific example of the configuration of this image information importing section. The active input operating mechanism 34 includes a PRDC generator 341 that generates a data read control signal PRDC and an AND gate 342. The passive input operating mechanism 35 is constituted by an AND gate 351. When the input request signal from the sequence control circuit 40 is not output, the AND gate 351 is in a prohibited state, and even if it receives the data write control signal PWTC, it does not return the response signal PACK and makes the external means stand by. It has become.

In the image information sending section, during active operation, the active output operation mechanism 37 outputs a data write control signal @PWTC to send out data, and a response signal PACK thereto terminates the sending operation. During passive operation, the passive output operation mechanism 38 receives an external data read control signal PRDC and ends the data sending operation. FIG. 4 shows a specific example of the configuration of this image information sending section. The active output operating device MA37 is a PWTC-generator 3 that generates a data write control signal PWTC.
71 and an AND gate 372. The passive output operating mechanism 35 is composed of an AND gate 351.

Enlargement/reduction circuit 1 equipped with image information mediating means as described above
1, a specific operational example of the mediating transfer of image information between the image buses I and II will be described below.

The specific bus configuration in this embodiment is as shown in FIG. 5, for example. Address buses 18 and 19 for accessing the image buffer memory 5 and display memory 6 are connected to ports A to A.
There are 26 lines of A25 and 16 lines of data bus 22.23.24.26 of Do=D1s. Control signal buses 19.21°25.27 include a data read control signal PRDC as a clock for image information transfer, a data write control signal PWTC, and a response signal PACK for these.
In addition to the horizontal line end signal HEND.

There are six in total, one for each control signal of the vertical end signal VEND, and one for the selection signal ADSEL of the two sets of address generation circuits 7.8.

First, the operation of displaying a document image stored in the image buffer memory 5 on the display will be explained. In the case of this image processing operation, the image buffer memory 5 is connected to the image bus ■, and the display memory 6 is connected to the image bus ■, so the data importing section side of the enlarging/reducing circuit 11 is connected to the image bus ■, and the data sending section side is connected to the image bus ■. Connection relationships are selected such that they are respectively connected to image bus ■. First, the enlargement/reduction circuit 11 having an image information mediating means has an active input operation mechanism 34 at an image information take-in section and a send-out section, respectively.
, is activated to activate the active output operating mechanism 37. When the enlargement/reduction circuit 11 starts operating, the active input operation mechanism 34 outputs a data read control signal PRDC to the image buffer memory 5 in which text image information is stored. One of the two sets of address generation circuits 7.8 is assigned to the address generation circuit that accesses the image buffer memory 5, and the address is sequentially updated in accordance with the data read control signal PRDC from the enlargement/reduction circuit 11. Response signal P to data read control signal PRDC
ACK is returned from the image buffer memory 5 on the PACK line, and the enlargement/reduction circuit 11 uses its active input operation mechanism 3.
4 takes in the image information from the image buffer memory 5 into the input data latch 32. The image information captured in this way is subjected to predetermined enlargement or reduction processing by the enlargement/reduction calculation mechanism 31.

The enlarged or reduced image information is sent out by the data write control signal PWTC output from the active output mechanism 37 of the same enlargement/reduction circuit 11 to the display memory 6. In this case as well, one of the address generation circuits 7.8 is assigned to access the display memory 6, and the addresses are sequentially updated in accordance with the data write control signal PWTC. A response signal PACK to this data write control signal PWTC is outputted from the display memory 6 onto the PACK line and taken in by the active output mechanism 37 of the enlargement/reduction circuit 11. As a result, the enlarging/reducing circuit 11 moves to the next sequence.

The timing of the above image information transfer is as shown in FIG.

Next, a case will be described in which text and image information is taken in from an external device via the image input/output means, written into the display memory 6, and displayed. The compression/expansion circuit 16 will be taken as an example of image input means.

When displaying document image information imported from an external device, if you want to display it at the same size as it was imported without equal parts,
The compression/expansion circuit 16 operates as an active operation means, sends out the transfer control signal by itself, and writes it into the display memory. However, especially in the case of display, the display size of a document image is limited due to various displays that interact with the system, and there are many cases where it is desired to display the document image in a reduced size. Conventionally, the method taken to meet this request is to separate only the display portion from the rest and perform scaling processing only when writing to the display memory. According to this method, flexible scaling is possible for display, but scaling processing is limited to display, and for example, it is possible to scale up or down a part of text image information stored in the image buffer memory. It becomes impossible to perform processes such as copying to the image buffer memory, or enlarging or reducing the document image stored in the image buffer memory and printing it out.

In this embodiment, there are two image buses 1. By having the above-described transfer mediating means in the enlargement/reduction circuit 11, it is possible to write document image information imported from the outside into the display memory 6 or the image buffer memory 5 as is. It is also possible to perform enlargement or reduction processing via the enlargement/reduction circuit 11 before writing. In the former case, the data write control signal P output from the compression/expansion circuit 16
The captured information is directly written into the display memory 6 by the WTC, and at this time the image information is transferred from the data bus 24 via the image bus switching control circuit 17 and then via the data bus 23. In the latter case, , :.

The passive input operation mechanism 35 of the enlargement/reduction circuit 11 is activated.
:,,' Data write control signal from compression/expansion circuit 16
'(i' bow size/No. 1 PWTC
Import 1 degree file, enlarge or reduce it, and then
, “1;.

・, 1 Output from the active output operation mechanism 37 of the enlargement/reduction circuit 11
, .;'・ The data write control signal PWTC is
, "1°" is written into the memory 6. That is, at this time, 5;.

The image information captured by the compression/expansion circuit 16 is
゛・j.

The data is transmitted from the data bus 24 through the enlargement/reduction circuit 11.
:, ゛) Enters J-tabus 26, image bus switching circuit 1
7, the signal is sent to the data bus 23, and written into the display memory 6.

As described above, according to the present embodiment, extremely flexible image processing is possible in terms of image information transfer between the image buffer memory 5 and display memory 6, writing of image information from the outside into the display memory 6, and the like. Moreover, as is clear from FIGS. 2 to 4, the image information transfer mediating means between the two image buses I and If is realized by extremely simple hardware.

By the way, as seen in the previous explanation, it is often necessary to perform enlargement/reduction processing on the document image information imported from the image input/output means before displaying it, but at the same time, it is necessary to perform some kind of processing on the document image information imported. For example, it may be necessary to copy a portion or overlay a small image. Alternatively, it may be necessary to successively change the reduction ratio of the same document image in order to set it in a state that is most easily viewed by the user. In this case, it is necessary to store the document image being displayed in the image buffer memory and read it out and display it or process the m-image collection as needed. Conventionally, this processing requires two phases: first, storing the document image information in the image buffer memory, and then displaying it, and therefore, sufficient processing speed cannot be obtained.

In the present invention, as already mentioned, there are two image buses 1 and II.
are provided and can operate independently, so that the document image sending means can simultaneously transfer images to a plurality of other means.

In the above operation example, 1. The document image information sent from the image input/output means can be transferred to the image buffer memory and the display memory at the same time. A problem with such simultaneous transfer is the difference in the capture speeds of the plurality of capture sides. In the present invention, this problem can be solved by arranging the respective response signals to the transfer lock to be logically ANDed on the image bus.

FIG. 7 is a diagram for explaining such an embodiment. In the figure, 61 is the PACK line on the control signal bus, 62+, 622.

623 respectively send a response signal P to this PACK line 61.
This is a PACK output stage of each means that outputs ACK. Each output stage is comprised of an open collector gate 63 and its movable control gate 64, and becomes movable when the enable signal EN is high.

With such a configuration, the response signal PAC issued by the plurality of means
The PACK line 61 does not go high while any one of KI to PACK3 is low, and PAC is not activated until the outputs of all PACK output stages 621 to 623 become high.
K line 61 becomes high. This makes it possible to maintain complete synchronization of image information transfer, allowing simultaneous transfer to multiple means.

Note that, instead of adopting the configuration of calculating logical product using a gate circuit as shown in FIG. 7, it is also possible to adopt a method in which, for example, only the response signal PACK of the means with the slowest response is returned to the PACK line. .

This is also substantially the same as performing a logical product on the same bus, and the same effect can be obtained.

Next, the configuration and operation of the memory access control circuit portion in the device of the present invention will be explained in more detail.

As shown in FIG. 1, this device uses two two-dimensional address generation circuits 7 in order to simultaneously control access to the image buffer memory 5 and the display memory 6.
and 8 are provided between the two image baths and .

Considering only the image information transfer between the image buffer 1 memory 5 and the display memory 6111, and the information transfer between these memories and other means, the two-dimensional address generation circuits 7 and 8 have one for the image buffer memory 5 and the other for the image buffer memory 5. may be fixedly connected to different image busses or (2) for the display memory 6, but in the embodiment of FIG.

■It can be connected to any of the following. This is so that image information can be transferred only within the image buffer memory 5 and only within the display memory 6. When transferring image information as described above, the image bus switching control circuit 17, scaling circuit 11, graphic processing circuit 12, scan/printer interface 15, compression/expansion circuit 16, etc. are used to write and read image information. It is only necessary to input and output only the control clock and image information for the image bus or (2), and there is no need to control access to the image buffer memory 5 or display memory 6.

FIG. 8 shows a schematic configuration of the two-dimensional address generation circuits 7 and 8. 71 connects this address generation circuit to CPU1.
72 is a register selected by the CPU 1 and set with a command CMD necessary for access control; 73x, 74x, 7
5x, 73y, 74Y, 75y are the same <Start address X selected by CPU1 and related to X and Y coordinates
These registers are set with 5TA, YSTA, the number of steps X5TP, YSTP, which is the minimum unit for calculating an address, and the number of repetitions XN and YN of address calculation. Counters 76x, 76y, timing control circuit 77, multiplexer 78X.

78Y, 7dar 79x, 79y are the parts that calculate the X, Y (D7 address. Multiplexer 78X.

Address data obtained from 78r is interface 8
It is designed to be output to address bus 18 or 20 via 0X and 80Y. 81x.

Reference numeral 81y is an interface for controlling the timing of outputting or stopping address data taken into this address generation circuit by a control signal sent from another device via the control bus 19.21.

These two two-dimensional address generation circuits 7 and 8 are connected to the image bus 1. The following describes the operation of the device connected to the II when performing basic editing processing for clothing, such as extracting an image from a certain area within one document and pasting it in another area.

FIG. 9 shows the extracted area in the document at this time with a solid line, the transfer destination area with a broken line, and shows the address relationship of each area. When performing such image editing, for example, one two-dimensional address generation circuit 7 accesses the transfer source area, and the other one accesses the transfer source area. Egae a l,,tsu,,e□68□□8auyayu ;l
□ is selected by the CPU, and the commands necessary for access control, the start address regarding the x and Y coordinates, the number of steps, the number of repetitions, etc. are set in each register, and access control becomes possible. Next, for example, when the data read control signal PRDC is output from the image bus switching control circuit 17 to the control bus 19 on the image bus side,
The two-dimensional address generation circuit 7 selected as the transfer source starts operating, calculates a predetermined address, and outputs it to the address bus 18 on the image bus side. As a result, the image buffer memory 5 connected to the image bus (2) side is accessed, and the image information in the transfer source area is read out and output to the data bus 22.

When the image bus switching control circuit 17 finishes taking in the transfer source image information from the data bus 22, it then outputs the data write control signal PWTC and the previously read image information to the control bus 19 and the data bus 22, respectively. Control signal P for data writing is sent to control bus 19.
When the WTC is output, the two-dimensional address generation circuit 7 stops outputting the address data of the transfer source, and the other two-dimensional address generation circuit 8, which has not been selected as the transfer destination, starts operating. This two-dimensional address generation circuit 8 is a converter.1. ′ Generate a destination address and connect it to the address bus
・) 18, thereby writing the image information to the transfer destination area of the image buffer memory 5. Once this writing process is complete, the next step is to write to the image bus.
6. The switching control circuit 17 outputs the data read control signal PRDC to the control bus 19 in order to read the next image information □ from the transfer source again, and performs the reading and extraction process in the same manner as described above. At this time, the two-dimensional address is generated. 'Mo, the circuit 8 stops outputting the transfer destination address, and the two-dimensional address generation circuit 7 generates the next address '9. : Calculate and output.
1.・By repeating the above read/write process over the entire predetermined area and sequentially, an eagle as shown in FIG. 9 is created.

No. 1 Two-dimensional and high-speed image information transfer within one document
- to be carried out. At this time, each address generation circuit 7
．． The address generation at step 8 is performed by following the flowchart shown in Figure 10.
, □'' 4. That is, in the case of image transfer as shown in FIG.
Start address (SXo, SY port), (DXo,
DYo), number of steps in X direction 5XSTP, DXST
Number of steps in P and Y directions: 5YSTP.

DYSTP, the number of repetitions in the X direction M, the number of repetitions in the Y direction N, etc. are set, and the main scanning direction is, for example, the X direction, and the
Access is performed by sequentially adding the number of steps in both directions. During this time, image transfer within the image buffer memory 5 is performed by the image bus switching control circuit 17 simply inputting and outputting image information and read and write control signals.

FIGS. 11(a) to (Q) show that image transfer can be performed in various ways by selecting the direction in which the two two-dimensional address generation circuits 7 and 8 generate addresses for the transfer source and transfer destination. In the image transfer shown in FIG. 9, both of the two address generation circuits use the main scanning direction as the X direction, and generate addresses by sequentially adding steps.
). In addition, as shown in the flowchart in Figure 10, the main scanning direction can be changed to the X direction or the Y direction.
' By specifying whether to select the address in the X direction and the address in the Y direction, and whether to sequentially add or subtract the number of steps from the start address,
As shown in various examples in FIG. 11, image editing such as 90° rotation, 180° rotation, horizontal reversal, vertical reversal, arbitrary angle rotation, etc. is possible.

In addition, in the image transfer example described above, a two-dimensional address generation circuit for the transfer source and a two-dimensional address generation circuit for the transfer destination are used.
Simple enlargement/reduction processing can be performed by simply changing the number of steps set in the address generation circuit.

In other words, if the number of steps at the source and destination is the same, an image of the same size will be transferred, but if the number of steps at the destination is set to 1/2 that of the source, the image at the destination will be the same as the source image. is 1/2
It will be reduced. In this case, there is no need to use the scaling function of the scaling circuit 11 shown in FIG.

Similar to image transfer within the image buffer memory 5, image transfer within the display memory 6 is also possible. Access control by the address generation circuits 7 and 8 in this case is performed using the address bus 20 and control bus 21 on the image bus ■ side, and image information is also transferred via the data bus 23 on the image bus ■ side. Ru.

In addition, at the same time as transferring image information between the image buffer memory 5 and the display memory 6 as described above, for example, writing an image from the scanner 13 to the image buffer memory 5, the graphic processing circuit 1
Image processing such as writing a character pattern from 2 to the display memory 6 and displaying it on the display can also be easily performed by access control by the two two-dimensional address generation circuits 7 and 8. In these image processes as well, the image bus switching control circuit 17, scanner/printer interface 15, graphic processing circuit 12, etc. simply handle reading and writing control signals and image information without being conscious of controlling access to each memory. Image information can be two-dimensionally stored in a predetermined area of each memory by simply transferring the image information to the necessary bus. Since the two two-dimensional address generation circuits 7.8 can each operate independently, they do not affect each other, and the direction and unit of address generation can be set independently. For example, when inputting an image from the scanner 13 to the image buffer memory 5 in units of 16 bits, the number of steps of the two-dimensional address generation circuit 7 selected for the image buffer memory 5 side is set to 16, while the number of steps of the graphic processing circuit 12 is set to 16. When writing image information into the display memory 6 in units of 8 pits, the number of steps of the two-dimensional address generation circuit 8 selected for the display memory 6 may be set to eight.

Also, the screen size in each memory (the vertical and horizontal width of the area)
may also be different.

By providing the two two-dimensional address generation circuits 7 and 8 between the two image buses (1) and (2) as described above, access control means are provided for each of the various means for transferring information to the image buffer memory and display memory. There will be no need. Furthermore, as mentioned above, since the two address generation circuits 7 and 8 are configured as exactly the same hardware, the scale of the control program and hardware can be reduced, and the development period can also be shortened. Further, by simply changing the commands and parameters for each of the two-dimensional address generation circuits 7 and 8, it is possible to perform various types of access control and execute various image editing processes as described above.

By the way, in Fig. 8, the output X and Y coordinate addresses are output as they are as two-dimensional addresses, but in reality, the X and Y coordinates of the two-dimensional area of the image are The address and Y address are given to the memory as a one-dimensional address as a lower address and an upper address of the memory, respectively. For example, as shown in FIG. 12(a), the memory space of 211 x 2" 2 (-2048 dots x 4096 dots) is normally 8 bits (
A one-dimensionally continuous memory space is constructed in units of 16 pits, etc.) as shown in FIG. 12(b). In this case, if the address is a bit address, then Ar.

~Aro (Ao is on the LSB side) is the X address, A22~A
11 (A22 is MSB side) as Y address and A22~
Just give An to the memory. In such a memory space,
For example, when an image of 1128 dots x 2400 dots (e.g., equivalent to an A4 size image of 8 dots/am) as shown by diagonal lines in Fig. 12(C) is stored in memory, the image actually becomes Fig. 12(d). As shown by diagonal lines, a portion of the continuous memory space is occupied in a discrete manner, resulting in poor memory usage efficiency.

In addition, when editing various image sizes, it is necessary to develop an editing program instead of directly reading the physical address depending on the implemented memory configuration.

It is inconvenient to improve, and flexible management of document images is difficult.

The present invention performs address control that solves these problems.

FIG. 13 shows an embodiment of an address generation circuit that solves this problem and allows the memory space expressed by -dimensional addresses to correspond to various image sizes so that it can always be used efficiently.

This configuration differs from the basic configuration in FIG. 8 in that it weights the Y address in accordance with the image size.

An XW register 83 set by the CPU 1 is provided,
This XW register 83 and multiplexers 78x, 78y
An address conversion circuit 82 is provided for generating continuous one-dimensional addresses using the output of the address converter 82.

FIG. 14 shows a specific configuration example of this address conversion circuit 82. Multiplier 821 multiplies (XW)X (Y) by ixw set in XW register 83 and Y address from multiplexer 78Y. Adder 822 is
The multiplication result of the multiplier 821 and the X address of the multiplexer 78x are added to calculate A-(XW)X (Y)+(X), thereby converting the two-dimensional address into a one-dimensional address. If the output A of this adder 822 is directly output to the address bus 18 or 20, the logical address of the memory becomes the physical address and the image buffer memory 5
Alternatively, it is given to the display memory 6 as a one-dimensional address. Since the above-mentioned value of XW is arbitrarily set depending on the image size at the time of editing, image information of an arbitrary-sized area can be continuously stored in a one-dimensional memory space using the above formula. That is, FIG. 12(C) and
゛Useless memory areas as shown in (d) can be eliminated. Furthermore, the output A of the adder 822 is converted to the conversion table 82.
By performing address conversion using 3, images of various sizes can be managed flexibly.

A specific example of image management using this address conversion will be described next. For example, as shown in FIG. 15, three parts images A, B, and C of different sizes are stored in the image buffer memory 5, and their physical and logical addresses are
Manages part numbers, etc. The part with number 1 is stored in a continuous area from physical address 0OOOOo to 01FFFH (hexadecimal), and the part with number 2 is stored in a continuous area with physical address 00OOOo to 01FFFH (hexadecimal).
Although it is stored in a continuous area from 20000H to 037FFF)l, the part with number 2 is logically managed as being stored at logical addresses 00000M-017FFFH. The same applies to the part numbered 3.

Let us now consider the case where part number 2 image flB is deleted and another part image is registered. When part number 2 is deleted, physical address o20000H~0 of image buffer memory 5 is deleted.
The area below 37FFFH and 070000H becomes a free area. However, since the physical addresses required to register a new component image are not consecutive, it has not been possible to register this using the deleted address area of the component surface 81B in the past. In the present invention, the conversion table 8 in FIG.
By rewriting the contents of 23, discrete areas can be treated as if they were continuous areas. In other words, in this case, the conversion table 823 is converted from physical addresses 038000o to 06FFFFu to 050 by CPtJl.
000H to 087FFFH, 070000) 1 to 08
Change 7FFFH to 038000H-04FFFFH. As a result, as shown in FIG. 16, a continuous address area can be secured for the component plane (IID), and component image information of component number 4 is newly added.

By rewriting the contents of the conversion table 823 in this way, parts and documents of various sizes can be managed and handled consistently, and the image buffer memory 5 and display memory 6 can be used effectively. In addition, conversion between logical addresses and physical addresses can be done flexibly, and complex parts management, memory management, etc. can be processed using logical addresses in the management program, thereby improving development efficiency and reliability of the management program.

FIG. 17 shows a schematic configuration of the conversion table 823 of the address conversion circuit 82 as described above. The RAM 8231 is a core memory of the conversion table 823 and stores conversion data. The write data port 8232, the write address port 823s, and the read address port 8234 are each three-state ports, and are turned on only when writing or reading conversion data. When writing conversion data, use the CPU, interface
The write address of the RAM 8231 is set as the write address port 823ae enable from 71, and the write data is written from the write data port 8232. At the initial stage, conversion data is written so that the read address from the adder 822 is outputted from the RAM 8231 without being passed through. For example adder 82
If the read address from 2 is 0OOOH~07FFH, the output of RAM8231 is also 0OOOH~07FF.
Write the conversion data so that it becomes H. Then the first
As shown in FIG. 6, when handling various parts, the contents of the RAM 8231 are rewritten as described above to output the necessary physical addresses in accordance with the management of each part.

For example, if AO-At 4 of addresses Aa to A25 is left unchanged and A1s to A2S can be mapped through the conversion table 823, part number 3 in FIG.
Set the physical address 038000H to part number 3 in Figure 16.
In order to make the physical address 050000H of the conversion table 823 RAM 8231 address 0
Just rewrite 007H to 0OOAH. If other data are sequentially rewritten in the same way, they will be mapped to physical addresses as shown in FIG.

In the concrete prototype example of the present inventors, the X address,
The Y address and XW are each 13 bits, and according to the above formula, 26 dots (in this case, the white image information is 102" - 64 Mbits, that is, the image up to AO is 8 dots/bit). (which can be handled) into a -dimensional address, and then the upper 11 bits are converted to a conversion table 823.
Converts a logical address to a physical address.

This makes it possible to map addresses in units of 4 bytes (1 byte - 8 bits), and in the case of 8 dots/m, it is possible to logically handle images of various sizes in units of 22.6 m square images. It is now possible to flexibly occupy and release memory areas of various sizes, divide one, merge two, and so on.

The address conversion circuit 82 is not limited to that shown in FIG. For example, the entire address conversion circuit 82 is stored in RAM or RO.
It can be configured with a memory such as M. In this case, the value of address conversion according to various image sizes is
Calculate the above formula in U1 etc. and store the value in RAM or R.
Write it to OM and use multiplexer 78x, 78y
Address conversion is performed with reference to the X address, Y address, and set value xW of the XW register 83, and the results are provided to the interfaces 80x and 80y. Further, the multiplier 821 in the address conversion circuit 82 may also be a multiplier-dedicated LSI, or may be configured by combining adders.

FIG. 18 shows the operation flow of the address conversion circuit 82 when the function of the multiplier 821 is realized using an adder. In this case, when the Y address is ±1, ±xW
After adding up and performing the multiplication process of (XW)X (Y),
Addition of (XW)x (Y)+(X) is performed. Furthermore, the conversion table 823 can be written at any time, during or before or after operation. Naturally, the units to be converted using the conversion table 823 are appropriately set depending on the performance, specifications, purpose, etc. of the device.

The invention is not limited to the embodiments described above. For example, as shown in FIG. 19, the scanner/printer interface 15 and the compression/expansion circuit 16 may also be connected to the image bus (2).

With this configuration, the enlargement/reduction circuit 111, the graphic processing circuit 12. Scanner/printer interface 15. The compression/decompression circuits 16 are all connected to two image buses (■ and ■), and each can access the image buffer memory 51 and display memory 6 using a free bus, increasing the flexibility of the entire system. , the speed is further increased.

Furthermore, the two two-dimensional address generation circuits 7 and 8 are integrated into one module, and internally have two systems of memory (image buffer memory and display memory, or transfer source and transfer destination in one memory). Access control may also be performed. In this case, one two-dimensional address generation circuit may be configured to output addresses for the image buffer memory 51 and the display memory 6 in a time-division manner. Furthermore, when transferring images between memories, it is sufficient to make the transfer source and transfer destination addresses the same and output them to each memory in a time-sharing manner. As a method for this time division, it is sufficient to provide two systems of output stages and latches from the address conversion circuit 82, and output enable the latched address at each output time to output it to the address bus. This further reduces the size and cost of the device.

Conversely, the two-dimensional address generation circuit may be configured with three or more modules to increase speed and flexibility.

Furthermore, if the image buffer memory 5 and display memory 6 are not IC memories but disk memories such as magnetic disks or optical disks, the addresses generated from the two-dimensional address generation circuit 7.8 are track numbers, sector numbers, disk memories, etc. It will be composed of information such as numbers. In this case as well, memory access control can be performed in the same manner as in the above-described embodiment. The same is true when further memory such as magnetic bubble memory or hologram memory is used.

Furthermore, by operating one of the two-dimensional address generation circuits 7.8 in combination with the image bus switching control circuit 10, simple graphic processing such as straight lines, diagonal lines, and filling in rectangular areas can be performed quickly and easily. can. For example, data "FO" (hexadecimal number) is set in the image bus switching control circuit 10, and the image bus switching control circuit 10 is set to "FO" (hexadecimal number).
O'' data and a data write control signal are output to the data bus 22 and control bus 19, respectively, and when the two-dimensional address generation circuit 8 sequentially outputs addresses to the address bus 20, the display memory 6 has a line width of 4. Bit straight lines can be drawn.

When data "80" is set in the image bus switching control circuit 10, a straight line with a line width of 1 bit can be drawn. Furthermore, when data "FF" is set, the specified area can be filled in with white or black.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall configuration of an embodiment of a document image processing device according to the present invention, FIG. 2 is a diagram showing the configuration of its enlargement/reduction circuit, and FIG. 3 is a diagram showing image concession in the enlargement/reduction circuit. FIG. 4 is a diagram showing an example of the configuration of the image information sending section, FIG. 5 is a diagram showing an example of the bus configuration in the configuration of FIG. 1, and FIG. 6 is a diagram showing the configuration of the control signal. Figure 7 is a diagram showing a timing chart; Figure 7 is a diagram showing an example of the configuration of a response signal sending unit for a control signal from another device using a plurality of means; Figure 8 is a diagram showing an example of the basic configuration of a two-dimensional address generation circuit; The figure is a diagram for explaining the operation of image transfer, Figure 10 is a diagram showing the flow of address generation in the address generation circuit, and Figure 11 (
a) to (Q) are diagrams showing various access control examples for image editing, FIGS. 12 (a) to (d) are diagrams for explaining the operation of normal one-dimensional address generation, and FIG. FIG. 14 is a diagram showing a specific configuration example of the two-dimensional address generation circuit in the embodiment of the present invention, FIG. 14 is a diagram showing a configuration example of the address translation circuit section, and FIGS. 15 and 16 are specific registration 17 is a diagram illustrating an example of the configuration of the conversion table in FIG. 14; FIG. 18 is a diagram illustrating the flow of one-dimensional address generation in the address conversion circuit;
FIG. 9 is a diagram showing the configuration of a document image processing apparatus according to Haku's embodiment. 1...CPtJ, 2...CPU memory, 3...Interface, 4...CPU bus, 5...Image buffer memory, 6...Display memory, 7.8...Two-dimensional address Generation circuit, 10... Vertical/horizontal conversion circuit, 11...
・Enlargement/reduction circuit (including information transfer mediating means), 12...
Graphic processing circuit, 13... Scanner, 14... Printer, 15... Scanner/printer interface, 1
6...Compression/expansion circuit, 17...Image bus switching control circuit, 18°20...Address bus, 22.23.24
．． 26...Data bus, 19.21.25.27...
- Control bus, 34... Active input operation mechanism, 3
5... Passive input operating mechanism, 37... Active output operating mechanism, 38... Passive output operating mechanism, 82... Address conversion circuit, 823... Conversion table. Applicant's representative Patent attorney Takehiko Suzue Figure 3, Figure 4, Figure 7. Transfer 7L Transfer 9 Figure 11 Transfer Spoon Matsudori Hirotransfer 7L Private Address X Atoshizu

Claims (1)

[Claims] An image buffer memory that temporarily stores document image information, a display memory that temporarily stores document image information to be displayed, an input/output means for document image information, an image bus used for transferring document image information, and manages and controls these. In the document image processing apparatus, there is provided two image buses that can operate independently as the image buses, and an image bus that controls connections between the image buffer memory and the display memory and the two image buses. A document image processing device comprising a switching control circuit.