JPS6236835A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS6236835A
JPS6236835A JP60176217A JP17621785A JPS6236835A JP S6236835 A JPS6236835 A JP S6236835A JP 60176217 A JP60176217 A JP 60176217A JP 17621785 A JP17621785 A JP 17621785A JP S6236835 A JPS6236835 A JP S6236835A
Authority
JP
Japan
Prior art keywords
pads
common
connecting lead
connection lead
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60176217A
Other languages
Japanese (ja)
Inventor
Fukunori Yamamoto
山本　福徳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP60176217A priority Critical patent/JPS6236835A/en
Publication of JPS6236835A publication Critical patent/JPS6236835A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07553—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To simplify the structure while preventing distortion of the circuit and oscillation, by disposing the respective grand pads very closely to each other, and electrically connecting the respective grand pads to a common external connecting lead by means of a common internal connecting lead which was bonded so as to extend over the two pads. CONSTITUTION:The respective grand pads 12a, 12b are disposed very closed to each other, and the respective grand pads 12a, 12b are connected to a common external connecting lead 13a by means of a common internal connecting lead 14 which was bonded so as to extend over the two pads. Since the common impedance is the sum of the parasitic resistances of the internal connecting lead 14 and the external connecting lead 13a, and the parasitic resistance of the internal connecting lead 14 is sufficiently small, the structure is simplified by performing the bonding by means of the common internal connecting lead 14. Further, if the slit portion 16 is shaped into comb teeth, the reliability is increased.

Description

【発明の詳細な説明】 （イ）産業上の利用分野 本発明は共通の外部接続リードに対して互いに独立した
複数のパッドを有する集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an integrated circuit device having a plurality of mutually independent pads for a common external connection lead.

（ロ）従来の技術 第４図は集積回路装置に組み込まれる一般的な増幅回路
を示し、（１）は集積回路装置に組み込まれる増幅回路
、（２）は入力端子、（３）は出力端子、（４）は電源
端子、（５）は接地端子、Ｑ、　、Ｑ、は前段増幅回路
１１を構成するＮＰＮトランジスタで、トランジスタＱ
１　のベースは入力端子（２）Ｋ、トランジスタＱ２の
エミッタは電源端子（４）に夫々接続される。(b) Conventional technology Figure 4 shows a general amplifier circuit built into an integrated circuit device, where (1) is an amplifier circuit built into an integrated circuit device, (2) is an input terminal, and (3) is an output terminal. , (4) are power supply terminals, (5) are ground terminals, Q, , Q are NPN transistors forming the front stage amplifier circuit 11, and transistor Q
The base of the transistor Q2 is connected to the input terminal (2) K, and the emitter of the transistor Q2 is connected to the power supply terminal (4).

Ｑ３、Ｑ４、・Ｑ、は複合ＰＮＰ型トランジスタ（７）
を構成するトランジスタで、Ｑ、はＰＮＰ型、Ｑ４、Ｑ
、はＮＰＮ型のトランジスタである。トランジスタＱ、
のベースはトランジスタＱ２のコレクタに接続されてい
る。Ｑａ　、Ｑ７は複合ＮＰＮ型トランジスタ（８）で
、トランジスタＱ６のベースは抵抗Ｒ８を介して電源端
子（４）・に接続されている。複合トランジスタ（７）
（６）はコレクタ接地コンプリメンタリ型の後段増幅回
路（９）を構成し、これはＢ級段として動作する。トラ
ンジスタＱ、のコレクタ、トランジスタＱ７のエミッタ
は出力端子（３）に接続されており、トランジスタＱ、
のエミッタは接地端子（５）Ｋ、　　）ランジスタＱ、
のコレクタは電源端子（４）Ｋ夫々接続される。Ｒ，、
Ｒ，は帰還抵抗である。Q3, Q4, and Q are composite PNP transistors (7)
The transistors that make up Q are PNP type, Q4, Q
, are NPN type transistors. transistor Q,
The base of is connected to the collector of transistor Q2. Qa and Q7 are composite NPN transistors (8), and the base of the transistor Q6 is connected to the power supply terminal (4) via a resistor R8. Composite transistor (7)
(6) constitutes a common-collector complementary type rear-stage amplifier circuit (9), which operates as a class B stage. The collector of transistor Q, and the emitter of transistor Q7 are connected to the output terminal (3), and the transistors Q,
The emitter of is the ground terminal (5) K, ) transistor Q,
The collectors of are connected to power supply terminals (4) and K, respectively. R,,
R, is a feedback resistance.

そして斯る回路、を集積回路装置罠組み込む場合、トラ
ンジスタＱ＊　、Ｑ−の各エミッタを共通のアルミニウ
ム蒸着配線で接続するとそこに存在する寄生抵抗が大で
あるために問題が生じる。この配線は引き回しが長くな
ることと幅２０μ、厚さ１．５μ前後に設計されること
が多いため、その寄生抵抗は数Ωに達することがあり、
これがトランジスタＱｔ　、Ｑｓの各エミッタと接地電
位との間に共通インピーダンスＲ４として介在すること
になり、後段増幅回路（９）で増幅された信号電流がそ
こに流れることにより生じる電圧降下が前段増幅回路（
６）に帰還され、不要な発振を誘発するのである。When such a circuit is incorporated into an integrated circuit device, a problem arises when the emitters of transistors Q* and Q- are connected by a common aluminum evaporated wiring because of the large parasitic resistance there. Because this wiring is often designed to have a long route and a width of 20μ and a thickness of around 1.5μ, its parasitic resistance can reach several Ω.
This is interposed as a common impedance R4 between the emitters of the transistors Qt and Qs and the ground potential, and the voltage drop caused by the signal current amplified in the second stage amplifier circuit (9) flowing there will be reduced to the first stage amplifier circuit (9). (
6) and induces unnecessary oscillation.

第を図は斯る不具合を解決した例であり、αυは集積回
路チップ、（１２ａ）（１２ｂ）は互いＫｆｉ立したグ
ランドパッド、（１２ｃ）は他のパッド、　　（１３ａ
）（１３ｂ）は外部接続リード、Ｑ４Ｉは内部接続リー
ドである。グランドパッド（１４ａ）（１２ｂ）はそれ
ぞれチップαυ上を延在するアルミニウム蒸着配線によ
りトランジスタＱ＊　、　Ｑ４の各エミッタに接続され
、　′且つ別々の内部接続リードＱ４１により共通の外
部接続リード（１３ａ）に接続されている。斯る構造に
よれば、トランジスタＱ２、Ｑｒの各エミッタが共通に
接続されるのは外部接続リード（１３ａ）上であり、共
通インピーダンスＲ３として介在するのは外部接続リー
ド（１３ａ）の抵抗分のみになるので、その値を充分小
さくして不要な歪、発振を防止できるのであるＣ特公昭
５２〜５２２８号公報に詳しい）。Figure 5 shows an example in which such a problem has been solved, where αυ is an integrated circuit chip, (12a) and (12b) are ground pads that are set at Kfi, (12c) is another pad, (13a)
) (13b) is an external connection lead, and Q4I is an internal connection lead. The ground pads (14a) (12b) are connected to the respective emitters of the transistors Q* and Q4 by aluminum evaporated wiring extending on the chip αυ, respectively, and are connected to the common external connection lead (13a) by a separate internal connection lead Q41. It is connected to the. According to this structure, the emitters of transistors Q2 and Qr are commonly connected on the external connection lead (13a), and only the resistance of the external connection lead (13a) is present as a common impedance R3. Therefore, the value can be made sufficiently small to prevent unnecessary distortion and oscillation (see details in Japanese Patent Publication No. 52-5228).

（ハ）発明が解決しようとする問題点 しかしながら、従来のものではグランドパッド（１２ａ
）（１２ｂ）各々にボンディングするために、夫々を相
当な距離だけ離間しなければならないので必然的にチッ
プ面積が大になるという欠点があった。更にまた、内部
接続リード（１４１本数が増加するのでワイヤボンディ
ング工程が煩雑になるという欠点があった。(c) Problems to be solved by the invention However, in the conventional one, the ground pad (12a
) (12b) In order to bond them to each other, they must be separated from each other by a considerable distance, which inevitably increases the chip area. Furthermore, since the number of internal connection leads (141) increases, there is a drawback that the wire bonding process becomes complicated.

に）問題点を解決するための手段 本発明は斯上した欠点に鑑みてなされ、回路の歪、発振
を防止しながら構造を簡単なものとした集積回路装置を
得ることを目的とし、各々のグランドパッド（１２ａ）
（１２ｂ）を極く近接して配設し、七の双方に跨るよう
にボンディングした共通の内部接続リードａ４により夫
々のグランドパッド（１２ａ）（１２ｂ）と共通の外部
接続リード（１３ａ）とを電気的に接続したことを特徴
とする。B) Means for Solving the Problems The present invention was made in view of the above-mentioned drawbacks, and aims to provide an integrated circuit device with a simplified structure while preventing circuit distortion and oscillation. Ground pad (12a)
(12b) are placed very close to each other, and a common internal connection lead A4 bonded across both of the pads connects the respective ground pads (12a) and (12b) to the common external connection lead (13a). It is characterized by being electrically connected.

（ホ）作用 本発明によれば、個別に設けたグランドパッド（１２ａ
）（１２ｂ）を共通の内部接続リードＩを介して外部接
続リード（１３ａ）と接続したので、内部接続リードＱ
４１を一本に省略できる他、グランドパッド（１２ａ）
（１２ｂ）を極く近接して配置するのでチップ面積を縮
小することができる。(E) Function According to the present invention, the individually provided ground pad (12a
) (12b) is connected to the external connection lead (13a) via the common internal connection lead I, so the internal connection lead Q
41 can be omitted to one, and the ground pad (12a)
(12b) are placed very close to each other, so the chip area can be reduced.

（へ）実施例 以下本発明による一実施例を図面を参照しながら詳細に
説明する。(F) Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

第１図及び第２図は本発明による集積回路装置の要部を
示し、ａυはその表面に第４図の増幅回路を形成した集
積回路チップ、（１２ａ）（１２ｂ）は極く近接して配
設したグランドパッド、（１２ｃ）は他のパッド、（１
３ａ）（１３ｂ）は外部接続リード、（１４１は内部接
続リード、ａ９は内部接続り〜ドロ４先端に形成したボ
ール部である。グランドパッド（１２ａ）（１２ｂ）は
夫々チップａυ上を延在するアルミニウム蒸着配線によ
りトランジスタＱ＝　、Ｑｉの各エミッタと接続され、
且つそれらの間には近接したことにより生ずる狭いスリ
ット部ＱＢを有する。外部接続リード（１３ａ）（１３
ｂ）は周知の如くリードフレームを用いて構成する。内
部接続リードＩは金細線をワイヤボンディングすること
により構成し、グランドパッド（１２ａ）（１２ｂ）に
おいてはボール部四がスリット部（ＩＦ５を跨ぐように
ボンディングすることＫより夫々のグランドパッド（１
２ａ）（１２ｂ）と共通の本発明の最も特徴とする点は
、夫々のグランドパッド（１２ａ）（１２ｂ）を極く近
接して配設し、その双方に跨がるようにボンディングし
た共通の内部接続リードＱ４１により夫々のグランドパ
ッド（１２ａ）（１２ｂ）と共通の外部接続リード（１
３ａ）とを接続した点にある。この構造によれば、以下
に説明する共通のインピーダンスＲ４を充分に小としな
がらもその構造を簡略化できる。共通のインピーダンス
Ｒ４はトランジスタＱ＝　、Ｑｉの各エミッタが共通に
接続された場所（ボール部０５になる）から接地電位が
印加される端子までの寄生抵抗であるから、本構造では
内部接続リードＩと外部接続リード（１３ａ）の寄生抵
抗の和になる。内部接続リード０４１の寄生抵抗は例え
ば直径２５μ、長さ０．３　ｃｔｎの金細線を用いると
約０，１５Ω、外部接続リード（１３ａ）の寄生抵抗は
例えば幅４ｍ、長さ１０＋ｍ。1 and 2 show the main parts of the integrated circuit device according to the present invention, aυ is an integrated circuit chip on which the amplifier circuit shown in FIG. 4 is formed, and (12a) and (12b) are very close to each other. The arranged ground pad (12c) is the other pad, (1
3a) (13b) are external connection leads, (141 is an internal connection lead, a9 is an internal connection ~ a ball portion formed at the tip of the drawer 4. Ground pads (12a) and (12b) each extend over the chip aυ. The emitters of transistors Q= and Qi are connected to each other by aluminum evaporated wiring,
Moreover, there is a narrow slit portion QB between them, which is caused by being close to each other. External connection lead (13a) (13
b) is constructed using a lead frame as is well known. The internal connection lead I is constructed by wire bonding thin gold wires, and in the ground pads (12a) and (12b), the ball portion 4 is bonded so as to straddle the slit portion (IF5).
The most characteristic feature of the present invention, which is common to 2a) and 12b, is that the respective ground pads (12a) and (12b) are disposed very close to each other, and a common The internal connection lead Q41 connects the respective ground pads (12a) (12b) and the common external connection lead (1
It is located at the point where 3a) is connected. According to this structure, the structure can be simplified while making the common impedance R4, which will be described below, sufficiently small. The common impedance R4 is a parasitic resistance from the place where the emitters of the transistors Q= and Qi are commonly connected (which becomes the ball part 05) to the terminal to which the ground potential is applied, so in this structure, the internal connection lead I and the parasitic resistance of the external connection lead (13a). The parasitic resistance of the internal connection lead 041 is, for example, about 0.15Ω when a thin gold wire with a diameter of 25μ and a length of 0.3 ctn is used, and the parasitic resistance of the external connection lead (13a) is, for example, 4m in width and 10+m in length.

厚さ０．３　ａｍの銅板を用いると約０．０００１５Ω
になるので、それらの和は約０．１５Ωであり、この値
は共通のインピーダンスＲ，として充分に小であると言
えるので、不要な発振を防止できる。Approximately 0.00015Ω when using a copper plate with a thickness of 0.3 am
Therefore, their sum is about 0.15Ω, and this value can be said to be sufficiently small as a common impedance R, so that unnecessary oscillation can be prevented.

即ち、本発明は外部接続リード（１３ａ）（１３ｂ）の
みならず内部接続リードａ４の寄生抵抗も充分に小であ
ることに基き、グランドパッド（１２ａ）（１２ｂ）個
々に内部接続リードα４をボンディングするのではなく
、共通の内部接続リードＩでボンディングすることによ
りその構造を簡略化するものである。That is, the present invention is based on the fact that the parasitic resistance of not only the external connection leads (13a) (13b) but also the internal connection lead a4 is sufficiently small, and the internal connection lead α4 is individually bonded to the ground pads (12a) (12b). Instead, the structure is simplified by bonding with a common internal connection lead I.

ここでグランドパッド（１２ａ）（１２ｂ）の双方を合
わせた大きさが他のパッド（１２ｃ）の面積と等しいか
またはやや大きいものとし、スリット部ＯｅＯ幅を数μ
に設計しておけば、ボール部０５１の大きさが約８０μ
前後になるのでボンダビリティには全く影響しない。更
にまた、スリット部０ｅの形状を第３図に示す如く櫛歯
状とし：′Ｇ１１５けば、より信頼度を増す。Here, it is assumed that the combined size of both ground pads (12a) and (12b) is equal to or slightly larger than the area of the other pad (12c), and the width of the slit portion OeO is several microns.
If the design is made, the size of the ball part 051 will be approximately 80μ.
Since it is before and after, bondability is not affected at all. Furthermore, if the shape of the slit portion 0e is made into a comb-like shape as shown in FIG. 3, the reliability will be further increased.

以上本発明を一般的な増幅回路のグランドバラ　　　　
　。The present invention has been described above as a ground balancer for a general amplifier circuit.
.

ド（１２ａ）（１２ｂ）について説明してきたが、本発
明は共通の外部接続リード（１３ａ）に接続すべき２個
以上のパッドを有するものであれば、例えば電子ボリュ
ーム回路においてその左右の回路で独立したグランドパ
ッドを設けたものでも実施可能である。Although the pads (12a) and (12b) have been described above, the present invention is applicable to circuits on the left and right sides of an electronic volume circuit, for example, as long as it has two or more pads to be connected to a common external connection lead (13a). It is also possible to implement the method with an independent ground pad.

（ト）発明の詳細 な説明した如く、本発明によればグランドパッド（１２
ａ）（１２ｂ）を極く近接して配設し、しかも双方合わ
せた面積が他のパッド（１２ｃ）と略等しい面積にする
ので、チ・ンプ面積を縮小できるという利点を有する。(G) As described in detail, according to the present invention, the ground pad (12
a) Since the pads (12b) are disposed very close to each other and their combined area is approximately equal to that of the other pad (12c), there is an advantage that the chip area can be reduced.

さらに複数のパッドに対して１本の内部接続リード（＋
４１で済むので、構造が簡略化され、ボンディング工程
の時間の短縮、コストダウンが計れるという利点を有す
る。そして特に第２の実施例においては、スリット部＋
１６）を櫛歯状としてあり、パターン認識する時に双方
のグランドパッド（１２ａ）（１２ｂ）を単一のパッド
として認識させることができるので、現状の機器をその
まま流用できるという利点をも有する。Additionally, one internal connection lead (+
41, the structure is simplified, and the bonding process time and cost can be reduced. In particular, in the second embodiment, the slit portion +
16) has a comb-teeth shape, and both ground pads (12a) and (12b) can be recognized as a single pad during pattern recognition, so there is also the advantage that current equipment can be used as is.

【図面の簡単な説明】[Brief explanation of the drawing]

第１乃至第３図はそれぞれ本発明を説明するための平面
図、断面図、平面図、第４図及び第５図はそれぞれ従来
例を説明するための回路図、平面図である。 主な図番の説明 （６）は前段増幅回路、　（２）は後段増幅回路、　０
１）は集積回路チップ、　　（１２ａ）（１２ｂ）はグ
ランドパッド、　　（１２ｃ）はその他のパッド、　　
（１３ａ）（１３ｂ）は外部接続リード、　（１４＋は
内部接続リード、側はスリット部である。 第１図 第２図 第３図 第４図 ｒ”−”−−−＝−−−”　４ 臣【− ■ 第５図1 to 3 are a plan view, a sectional view, and a plan view, respectively, for explaining the present invention, and FIGS. 4 and 5 are a circuit diagram, and a plan view, respectively, for explaining a conventional example. Explanation of the main drawing numbers (6) is the front stage amplifier circuit, (2) is the rear stage amplifier circuit, 0
1) is an integrated circuit chip, (12a) and (12b) are ground pads, (12c) are other pads,
(13a) (13b) are external connection leads, (14+ is an internal connection lead, and the side is a slit part. Figure 1 Figure 2 Figure 3 Figure 4 r"-"---=---" 4 Minister [- ■ Figure 5

Claims (1)

【特許請求の範囲】[Claims] （１）共通の外部接続リードに対して互いに独立した複
数のパッドを有する集積回路装置において、前記夫々の
パッドを極く近接して配設し、その双方に跨がるように
ボンディングした共通の内部接続リードにより前記夫々
のパッドと前記共通の外部接続リードとを電気的に接続
したことを特徴とする集積回路装置。(1) In an integrated circuit device having a plurality of mutually independent pads for a common external connection lead, a common An integrated circuit device, wherein each of the pads and the common external connection lead are electrically connected by an internal connection lead.
JP60176217A 1985-08-09 1985-08-09 Integrated circuit device Pending JPS6236835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60176217A JPS6236835A (en) 1985-08-09 1985-08-09 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60176217A JPS6236835A (en) 1985-08-09 1985-08-09 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6236835A true JPS6236835A (en) 1987-02-17

Family

ID=16009668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60176217A Pending JPS6236835A (en) 1985-08-09 1985-08-09 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6236835A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0946980A4 (en) * 1996-08-23 2001-04-18 Micro Devices Corp California IMPROVED INTEGRATED CIRCUIT STRUCTURES AND METHODS FOR FACILITATING ACCURATE MEASUREMENT OF INTEGRATED CIRCUIT DEVICES
JP2008298159A (en) * 2007-05-31 2008-12-11 Jatco Ltd Flow control structure and valve body

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0946980A4 (en) * 1996-08-23 2001-04-18 Micro Devices Corp California IMPROVED INTEGRATED CIRCUIT STRUCTURES AND METHODS FOR FACILITATING ACCURATE MEASUREMENT OF INTEGRATED CIRCUIT DEVICES
JP2008298159A (en) * 2007-05-31 2008-12-11 Jatco Ltd Flow control structure and valve body

Similar Documents

Publication Publication Date Title
US4403240A (en) Integrated circuit with at least three ground pads
JPH06186254A (en) Chip-type resistor for current detection
JP2924910B2 (en) Offset / trim circuit of differential amplifier
JPS6236835A (en) Integrated circuit device
JPH11121683A (en) Semiconductor integrated circuit
JP3019918B2 (en) Semiconductor integrated circuit and power supply circuit thereof
JP3386144B2 (en) Full bridge integrated circuit with four transistors
JP2824360B2 (en) Semiconductor device for current detection
JPH04349640A (en) Analog-digital hybrid integrated circuit device package
JP3158078B2 (en) Filter circuit
JPS6043682B2 (en) signal amplifier
JPS6415949A (en) Semiconductor integrated circuit for audio amplification
JP3067311B2 (en) Method of selecting one of a plurality of input signals according to control of potential of output terminal and output circuit
JPS6141249Y2 (en)
JPS5910253A (en) Semiconductor integrated circuit device
JPH063840B2 (en) Semiconductor device
JPH0548003A (en) Semiconductor integrated device
JPH0945865A (en) Hybrid integrated circuit device
JP2811740B2 (en) Integrated circuit
JPS5873213A (en) Current mirror circuit
JPS63204187A (en) Semiconductor radiation detection device
JPS6230701B2 (en)
JPH0646694B2 (en) Integrator circuit
JPH0637253A (en) Semiconductor integrated circuit
JPH01304748A (en) Ecl gate array