JPS6236936A - Timing extraction circuit - Google Patents

Abstract

PURPOSE:To improve accuracy and to reduce an occupied area by providing plural capacitors, plural analog switches and plural comparators to evade the direct effect of a threshold value of a field effect transistor. CONSTITUTION:When an input signal ei is below a positive reference voltage +Vref and over a negative reference voltage -Vref, a switch control signal E1 from a comparator 2 turns on an analog switch 5. Thus, the output signal eo of an operational amplifier 1 is zeroed always via an analog switch 4. When the signal ei is higher than the voltage V-Vref, the switch 5 is turned off and the output signal eo of the amplifier 1 reaches a value of ei-(+Vref) via the comparator 3, the switch 4 and a capacitor 7. When the signal ei is lower than the voltage -Vref, the switch 4 is turned off and the absolute value of a voltage being the subtraction of the voltage V-Vref from the signal ei appears as the signal eo. Thus, the accuracy is improved and the occupied area is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timing extraction circuit that extracts timing from a waveform equalized by 9 in 9 communication lines.

[Conventional technology]

The purpose of this type of timing extraction circuit is to provide the equalized signal waveform with a point in time at the center of the eye diagram for correct identification. Therefore, the timing component is extracted from the received code sequence itself. Particularly when the code format is bipolar, full-wave rectification of the received signal makes it unipolar, resulting in bright line spectrum components. Therefore, as shown in FIG.

Conventional timing extraction circuits consist of a full-wave rectifier circuit that generates a timing clock and a click circuit that removes timing jitter. It consists of a circuit. FIG. 4 shows waveforms of various parts of the timing extraction circuit shown in FIG. 3.

With reference to FIGS. 3 and 4, the above-mentioned full-wave rectifier circuit is
Operational amplifiers 9 and 10. Resistor 15゜16.17,18
．． and 19. It is composed of field effect transistors 12 and 13.

When the input signal e1 is positive, the diode-connected field effect transistor 12 is reverse biased and turned off (
OFF). When the field effect transistor 12 is turned off, the first operational amplifier 9, the input resistor 15, and the feedback resistor 16 form a 9-inverting feedback circuit. In this case, the values of resistor 15 and resistor 16 are equal to 1. <If set,
The gain is -1.

As a result, the output of amplifier 9 becomes -e1.

On the other hand, when the input signal ei is positive, the diode-connected field effect transistor 13 becomes forward biased, and the second operational amplifier 10, input resistor 17, and feedback resistor 19 form a 9-inverting feedback circuit.

The input signal of this inverting feedback circuit becomes -e1. Here, if the value of the resistor 17 is set to 1/2 of the value of the resistor 19, and the value of the resistor 18 is set equal to the value of the resistor 19.

The gains are added to -1, and the output of the operational amplifier 10 becomes el.

Next, when the input signal e1 is seven times negative, the field effect transistor 12 becomes forward biased.

The input and output of the operational amplifier 9 are short-circuited, and the output is always zero. On the other hand, the field effect transistor 13 is reverse biased and turns off, so the 1 operational amplifier 1
The gain of 0 is determined by the resistor 18.19. As described above, the values of the resistors 18 and 19 are set equal to 9, so the gain of the operational amplifier 10 is -1, and the 9-inverted waveform e1 is output. Therefore, as shown in Figure 4,
When the input signal e1 is positive, el is output to the output E3 of the second operational amplifier 10, and similarly when eo is negative, el is output to the output E3, resulting in a full-wave rectified waveform. .

Next, the Kuritsuno R circuit has a resistor 20 and a reference voltage for bias. diode-connected transistor 14 given f
, and Muffer 11. Second operational amplifier 1
If the voltage of the output E3 of 0 is higher than the reference voltage terminal ■r8f, the diode-connected transistor 14 is turned off (OFF).
Therefore, the voltage of the output E3 of the second operational amplifier 10 is the output e of the buffer 11. appears in

On the other hand, when the voltage of the output E3 of the second operational amplifier 10 is lower than the reference voltage Vref, the diode-connected transistor 14 is turned ON, and as a result, the buffer 11
The input voltage of becomes +vref, and this +V. f is the output e of the buffer 11. appears in In this way, the clicker outputs only the waveform that is higher than the reference voltage ref.

In this way, the conventional timing extraction circuit shown in FIG. 3 extracts the full-wave rectified waveform E3 of the input signal ei as shown in FIG.
is generated, clipped with +vr8f to the 9th order, and output e. I am getting .

[Problem that the invention seeks to solve]

However, since the above-mentioned conventional timing extraction circuit has a large number of resistances, there is a problem in that the area it occupies becomes large when it is realized on an MO8LSI.

Further, the threshold voltage of a field effect transistor depends on the manufacturing process, such as the impurity implantation density. Therefore, variations occur in the threshold voltage due to the difference between LSIs, and even if the reference voltage vr8f is constant, the clip level is different for each LSI.
The problem is that it varies depending on the situation.

[Means for solving problems]

The present invention includes an operational amplifier, a first capacitor having one end connected to a first input of the operational amplifier and an input signal input to the other end, and a first capacitor having one end connected to a second input of the operational amplifier. ,
a second capacitor to which the input signal is input at the other end; a third capacitor having one end connected to the output of the operational amplifier and the other end connected to the first input of the operational amplifier; a first comparator that compares the input signal with a first reference voltage;
a second comparator that compares the input signal with a second reference voltage; the output of the first comparator is used as a control signal; one end is grounded and the other end is connected to a second input of the operational amplifier; A second analog switch is connected in parallel to the third capacitor, and the control output is the output of the second comparator, and the output of the operational amplifier is connected to the tank. This timing extraction circuit is characterized in that it obtains a circuit drive signal.

〔Example〕

Next, the present invention will be explained with reference to one drawing.

FIG. 1 shows an embodiment of a timing extraction circuit according to the present invention. FIG. 2 shows input signals ei, switch control signal El, and E2. Output signal e. FIG.

Referring to FIGS. 1 and 2, 1 is an operational amplifier.

2 and 3 are comparators, 4 and 5 are analog switches.

6.7 and 8 are capacitances, El and E2 are switch control signals, +vref is a positive reference voltage, -Vr8f is a negative reference voltage, ei is an input signal + eo is an output signal 0 The above-mentioned timing extraction circuit The output state of is the input signal e1
It is divided into the following three states depending on the level.

(1) When the input signal e1 is less than the positive reference voltage +vr8f and more than the negative reference voltage -vr8f, (2) When it is higher than the positive reference voltage Vref, (3) When the negative reference voltage -
This is the case when Vr is lower than 8f.

First, (1) If −Vr8f≦e1≦10■ref,
The switch control signal E1 from the comparator 2 turns on the analog switch 5. Therefore, the non-inverting input of operational amplifier 1 is grounded. On the other hand, the switch control signal E2 from the comparator 3 turns on the analog switch 4. Therefore, operational amplifier 1 becomes full feedback. As a result, the output signal eo of the operational amplifier 1 is always zero.

Next, if + (2) e 1 > + Vref,
Comparator 2 is.

ei>+vr8f, and the switch control signal E1 from the comparator 2 turns off the analog switch 5. On the other hand, the comparator 3 determines that ei>-vref.

The switch control signal E2 from the comparator 3 turns on the analog switch 4. At this time, charge is accumulated in the capacitor 7 in a state where the input signal e1 is equal to the positive reference voltage +Vr8f. Therefore, the output signal e of the operational amplifier 1 becomes a non-inverting circuit with a gain of 1.

becomes the direct value of ei (10 vref).

Finally, * (3) When ei <"ref, the switch control signal E1 from the comparator 2 turns on the analog switch 5, and the non-inverting input of the operational amplifier 1 is grounded. On the other hand, to!, Switch control signal E of comparator 3
2 with analog switch 4 turned off.

As a result, the operational amplifier 1 has a configuration of an inverting feedback circuit.

The phase of the output from operational amplifier 1 is inverted.

It has a gain determined by the ratio of capacitance 6 to capacitance 8. At this time capacity 6
Charge is accumulated in the state where the input signal ei is equal to the negative reference voltage -vref. Therefore, the value l et -(-vref) l is added to the inverting input of the operational amplifier 1. At this time, if the values of the capacitors 6 and 8 are set equal, the gain of the operational amplifier 1 is -1, and the output signal e. The absolute value of the voltage obtained by subtracting the negative reference voltage -vr8f from the input signal ei appears.

Therefore, as shown in FIG. 2, when the input signal e1 is higher than the positive reference voltage +vref, it is clipped by +10vref, and the output signal e. Therefore, when the input signal is a signal higher than the positive reference voltage +vref, and the input signal e1 is lower than the negative reference voltage -vref.

The output signal e is clipped by l−■refl. for.

A signal below the negative reference voltage of the input signal e1 -r8f appears inverted.

〔Effect of the invention〕

As explained above, since the timing extraction circuit according to the present invention uses a capacitor, an analog switch, and a comparator, it is not directly affected by the threshold value of a field effect transistor as in the conventional case.

Therefore, the accuracy is higher than that of conventional timing extraction circuits. Furthermore, since no resistor is used, the area occupied can be reduced compared to conventional timing extraction circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the timing extraction circuit according to the present invention, FIG. 2 is a diagram showing waveforms of each part of FIG. 1, FIG. 3 is a circuit diagram showing a conventional timing extraction circuit, and FIG. The figure is a diagram showing waveforms at various parts in FIG. 3. 1... operational amplifier, 2, 3... comparator, 4, 5...
・Analog switch, 6 to 8... Capacity, 9.10...
・Operation amplifier, 11・・Buffer amplifier, 12-14・
...Field effect transistor, 16-20...Resistor. Figure 1 Figure 2

Claims (1)

[Claims] 1. an operational amplifier; a first capacitor having one end connected to a first input of the operational amplifier and an input signal being input to the other end;
a second capacitor having one end connected to the second input of the operational amplifier and the other end receiving the input signal; and a second capacitor having one end connected to the output of the operational amplifier and the other end connecting the first a third capacitor connected to the input of the input signal, a first comparator that compares the input signal with a first reference voltage, and a second comparator that compares the input signal with a second reference voltage. and the output of the first comparator is used as a control signal, one end of which is grounded,
a first analog switch whose other end is connected to the second input of the operational amplifier; and a second analog switch which uses the output of the second comparator as a control signal and is connected in parallel to the third capacitor. A timing extraction circuit comprising: a timing extraction circuit characterized in that a tank circuit drive signal is obtained from the output of the operational amplifier.