JPS6310566U - - Google Patents

Info

Publication number
JPS6310566U
JPS6310566U JP1986104310U JP10431086U JPS6310566U JP S6310566 U JPS6310566 U JP S6310566U JP 1986104310 U JP1986104310 U JP 1986104310U JP 10431086 U JP10431086 U JP 10431086U JP S6310566 U JPS6310566 U JP S6310566U
Authority
JP
Japan
Prior art keywords
heat sink
groove
external terminal
semiconductor substrate
solder pool
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986104310U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986104310U priority Critical patent/JPS6310566U/ja
Publication of JPS6310566U publication Critical patent/JPS6310566U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires
    • H10W72/5475Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第1図は本考案の要部を示す上面図、第2図は
その一部の断面図、第3図は本考案の他の例を示
す上面図、第4図は第3図の断面図、第5図は本
考案に係る装置の概略を示す断面図、第6図は本
考案に係る装置の概要を示す上面図、第7図は従
来装置の一部を示す上面図、第8図乃至第10図
はその製造課程を示す断面図である。

Claims (1)

    【実用新案登録請求の範囲】
  1. Fe製のヒートシンクに固着する半導体基板周
    囲に環状の溝を設け、この溝を囲む前記Fe製ヒ
    ーシンクに前記半導体基板と電気的に接続するC
    u製の外部端子を機械的に固定し、この外部端子
    を固着する半田の溜り部を前記Fe製ヒートシン
    クに設け、この半田溜り部と前記溝間を不連続に
    する前記Fe製ヒートシンク露出部を形成し、こ
    の露出部に近接する前記Fe製ヒートシンクに第
    2の溝部を設置し、このFe製ヒートシンクを被
    覆する封止樹脂部を具備することを特徴とする樹
    脂封止型半導体装置。
JP1986104310U 1986-07-09 1986-07-09 Pending JPS6310566U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986104310U JPS6310566U (ja) 1986-07-09 1986-07-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986104310U JPS6310566U (ja) 1986-07-09 1986-07-09

Publications (1)

Publication Number Publication Date
JPS6310566U true JPS6310566U (ja) 1988-01-23

Family

ID=30977686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986104310U Pending JPS6310566U (ja) 1986-07-09 1986-07-09

Country Status (1)

Country Link
JP (1) JPS6310566U (ja)

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