JPS6310571U - - Google Patents

Info

Publication number
JPS6310571U
JPS6310571U JP1986103777U JP10377786U JPS6310571U JP S6310571 U JPS6310571 U JP S6310571U JP 1986103777 U JP1986103777 U JP 1986103777U JP 10377786 U JP10377786 U JP 10377786U JP S6310571 U JPS6310571 U JP S6310571U
Authority
JP
Japan
Prior art keywords
semiconductor element
circuit
substrate
substrate via
conductive connector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986103777U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986103777U priority Critical patent/JPS6310571U/ja
Publication of JPS6310571U publication Critical patent/JPS6310571U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】
第１図は本考案による半導体素子の実装構造を
示す断面図、第２図は従来の実装構造の断面図で
ある。 １……第１の半導体素子、２……基板、３……
導電性コネクタ、４……半田、５……配線、６…
…第２の半導体素子、７……バンプ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 第１の半導体素子を導電性コネクタを介して基
    板に電気的に接続し、前記第１の半導体素子と前
    記基板との間に第２の半導体素子を配置し、該第
    ２の半導体素子の回路が形成された面はバンプを
    介して前記第１の半導体素子または前記基板のど
    ちらか一方に、回路が形成されていない面は接着
    部材を介して他方に接続したことを特徴とする半
    導体素子の実装構造。
JP1986103777U 1986-07-08 1986-07-08 Pending JPS6310571U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986103777U JPS6310571U (ja) 1986-07-08 1986-07-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986103777U JPS6310571U (ja) 1986-07-08 1986-07-08

Publications (1)

Publication Number Publication Date
JPS6310571U true JPS6310571U (ja) 1988-01-23

Family

ID=30976657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986103777U Pending JPS6310571U (ja) 1986-07-08 1986-07-08

Country Status (1)

Country Link
JP (1) JPS6310571U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8748229B2 (en) 2008-06-11 2014-06-10 Fujitsu Semiconductor Limited Manufacturing method including deformation of supporting board to accommodate semiconductor device
JP2018530923A (ja) * 2015-10-16 2018-10-18 ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ インターポーザなし積層ダイ相互接続

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8748229B2 (en) 2008-06-11 2014-06-10 Fujitsu Semiconductor Limited Manufacturing method including deformation of supporting board to accommodate semiconductor device
JP2018530923A (ja) * 2015-10-16 2018-10-18 ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ インターポーザなし積層ダイ相互接続

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