JPS6172848U - - Google Patents

Info

Publication number
JPS6172848U
JPS6172848U JP1984156904U JP15690484U JPS6172848U JP S6172848 U JPS6172848 U JP S6172848U JP 1984156904 U JP1984156904 U JP 1984156904U JP 15690484 U JP15690484 U JP 15690484U JP S6172848 U JPS6172848 U JP S6172848U
Authority
JP
Japan
Prior art keywords
circuit board
pattern
semiconductor device
adhesive film
conductive adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984156904U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984156904U priority Critical patent/JPS6172848U/ja
Publication of JPS6172848U publication Critical patent/JPS6172848U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】
第1図は本考案の半導体装置の一実施例を示す
主要断面図。第2図は本考案のバンプ付回路基板
の断面図。第3図は本考案のハーフエツチによる
回路基板の断面図。第4図は従来の半導体装置の
主要断面図。 1…IC、2…ICの各端子、3…回路基板の
絶縁部分、4…回路基板パターンのバンプ部分、
5…異方性導電接着膜、6…異方性導電接着膜に
散在するハンダボール、7…回路基板パターンの
メツキによるバンプ部分、8…回路基板パターン
、9…回路基板パターンのハーフエツチ部分、1
0…ICのバンプ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 異方性導電接着膜を用いてICと回路基板を実
    装する構造でICの各端子と相対応する回路基板
    の各パターン部分を断面的にもり上げる様にし、
    なおかつ、IC外部用部分と回路基板パターンと
    の間隙を15μm以上とることを特徴とする半導
    体装置。
JP1984156904U 1984-10-17 1984-10-17 Pending JPS6172848U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984156904U JPS6172848U (ja) 1984-10-17 1984-10-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984156904U JPS6172848U (ja) 1984-10-17 1984-10-17

Publications (1)

Publication Number Publication Date
JPS6172848U true JPS6172848U (ja) 1986-05-17

Family

ID=30714910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984156904U Pending JPS6172848U (ja) 1984-10-17 1984-10-17

Country Status (1)

Country Link
JP (1) JPS6172848U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999000842A1 (fr) * 1997-06-26 1999-01-07 Hitachi Chemical Company, Ltd. Substrat pour montage de plaquettes a semi-conducteur

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999000842A1 (fr) * 1997-06-26 1999-01-07 Hitachi Chemical Company, Ltd. Substrat pour montage de plaquettes a semi-conducteur

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