JPS6146769U - 電子回路形成チツプ搭載装置 - Google Patents

電子回路形成チツプ搭載装置

Info

Publication number
JPS6146769U
JPS6146769U JP1984131623U JP13162384U JPS6146769U JP S6146769 U JPS6146769 U JP S6146769U JP 1984131623 U JP1984131623 U JP 1984131623U JP 13162384 U JP13162384 U JP 13162384U JP S6146769 U JPS6146769 U JP S6146769U
Authority
JP
Japan
Prior art keywords
chip mounting
electronic circuit
circuit forming
mounting substrate
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984131623U
Other languages
English (en)
Inventor
正信 大畑
雅美 徳光
克彦 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1984131623U priority Critical patent/JPS6146769U/ja
Publication of JPS6146769U publication Critical patent/JPS6146769U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は、本考案による電子回路形成チップ搭載装置の
第１の実施例を示す略線的断面図である。 第２図及び第３図は、それぞれ、従来の電子回路形成チ
ップ搭載装置の実施例を示す略線図である。 第４図は、第１図に示す本考案による電子回路形成チッ
プ搭載装置の第１の実施例の要部の略線的平面図である
。 第５図、第６図及び第７図は、それぞれ本考案による電
子回路形成チップ搭載装置の第２、第３及び第４の実施
例を示す略線的断面図である。

Claims (1)

  1. 【実用新案登録請求の範囲】 上面に、接続用パッドを延長させている配線層を設けて
    いるチップ搭載用基板と、電子回路を形成し且つ上面乃
    至側面に接続用パッドを望ませている板状の電子回路形
    成チップとを有し、上記電子回路形成チップが、その下
    面を接着剤を用いて上記チップ搭載用基板の上面に固着
    させて、上記チップ搭載用基板上に固定して搭載され、
    上記電子回路形成チップの接続用パッドが上記チップ搭
    載用基板の接続用パッドに電気的に接続されている構成
    を有する電子回路形成チップ搭載装置において、 上記電子回路形成チップの接続用パッド上から、上記電
    子回路形成チップの側面上及び上記チップ搭載用基板の
    上面上をそれらの順に通って、上記チップ搭載用基板の
    接続用パッド上まで延長している絶縁層と、 上記電子回路形成チップの接続用パッド上から、上記絶
    縁層上を通って、上記チップ搭載用基板の接続用パッド
    上まで延長している導電性層とを有することを特徴とす
    る電子回路形成チップ搭載装置。
JP1984131623U 1984-08-30 1984-08-30 電子回路形成チツプ搭載装置 Pending JPS6146769U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984131623U JPS6146769U (ja) 1984-08-30 1984-08-30 電子回路形成チツプ搭載装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984131623U JPS6146769U (ja) 1984-08-30 1984-08-30 電子回路形成チツプ搭載装置

Publications (1)

Publication Number Publication Date
JPS6146769U true JPS6146769U (ja) 1986-03-28

Family

ID=30690202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984131623U Pending JPS6146769U (ja) 1984-08-30 1984-08-30 電子回路形成チツプ搭載装置

Country Status (1)

Country Link
JP (1) JPS6146769U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173214A (ja) * 2004-12-14 2006-06-29 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4899653A (ja) * 1972-03-31 1973-12-17
JPS5383462A (en) * 1976-12-28 1978-07-22 Seiko Instr & Electronics Ltd Production of semiconductor device
JPS60244035A (ja) * 1984-05-17 1985-12-03 Toshiba Corp 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4899653A (ja) * 1972-03-31 1973-12-17
JPS5383462A (en) * 1976-12-28 1978-07-22 Seiko Instr & Electronics Ltd Production of semiconductor device
JPS60244035A (ja) * 1984-05-17 1985-12-03 Toshiba Corp 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173214A (ja) * 2004-12-14 2006-06-29 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

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