JPS63121966A - Controller - Google Patents

Abstract

PURPOSE:To prevent a multi-CPU system from developing the confusion of a control action by constituting a reset release means so that it can generate a reset release signal for a host CPU behind a reset release signal for slave CPUs. CONSTITUTION:The reset release means 3 is designed to release the reset CPUs 1, 2a and 2b and to make them operable. The means 3 is made up of a reset circuit 4 connected to the CPUs 1, 2a and 2b and a delay circuit 5 placed between the reset circuit 4 and the host CPU 1. The delay circuit 5 employs a CR time constant circuit utilizing the charge and discharge of a resistance R3 and a capacitor C2, and the delay circuit 5 and the reset circuit 4 are connected to the same power source Vcc. After the reset release signals are inputted to the master CPU 2a and the scanner CPU 2b, the another reset release signal is inputted to the host CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device installed in a copying machine or the like, and particularly to a control device incorporating a plurality of CPUs.

A control device equipped with a host CPU and a plurality of slave CPUs that communicate with the host CPU is a so-called "multi-CPU".
It is widely used in copying machines and the like as the "U system".

In a copying machine equipped with such a multi-CPU system, when the power is turned on or when a paper jam is cleared, an operation such as canceling the system reset and setting all CPUs to an active state is performed.

Conventionally, when canceling the system reset of such a multi-CPU system, all CPUs are reset at the same time, but due to design errors in the reset canceling means and factors over time, all CPUs It is difficult to achieve an ideal state in which both are reset and released at the same time.
The mask CPU is reset first, or one of the slave CPUs becomes active first, then the host CPU becomes active, and then the remaining slave CPUs become active. Situations often occurred.

However, in such a case, there are the following problems. In other words, ■ After the host CPU becomes active, the slave CPU
When U becomes active, the host CPU
Although slave C is sending data to U
PU cannot receive and as a result slave CP
There is a risk that U will become a data block and cause confusion in control operations, etc.

■If any one slave CPU becomes active first, then the host CPU becomes active, and then the other slave CPUs become active, then the first slave CPU becomes active. Although the CPIJ can take in all the data from the host CPU, other slave CPUs that have become active after a delay will run out of data for the same reason as in (2), which may cause confusion in control operations, etc.

There were problems such as.

The present invention solves these conventional problems and provides multi-C
It is an object of the present invention to provide a control device that does not cause confusion in control operations as described above in a PU system.

5. Measures to Solve the Problems In order to achieve the above object, the present invention provides a host CPU,
a plurality of slave CPUs communicating with the host CPU;
A control device comprising reset release means for releasing the reset state of the host CPU and slave CPU, wherein the reset release means issues a reset release signal to the host CPU with a delay from a reset release signal to the slave CPU. The main point is that

According to the above configuration, the reset release signal to the host CPU is issued with a delay from the reset release signal to the slave CPU, so the slave CPU is always in the active state before the host CPU becomes active. state. Therefore, all the data sent by the host CPU is received by the slave CPU, and the control device does not suffer from timing lag during communication.

The above-mentioned reset canceling means may be a combination of a reset circuit and a delay circuit, or a system in which delay circuits are connected to the CPU separately, and the time constant of the delay circuit connected to the CPU is connected to the slave CPU. There are some that are set larger than the time constant of the delay circuit, and will be explained in detail in the following embodiments.

Figure 1 is a diagram showing an outline of a control device installed in a copying machine or the like as an example of the present invention, where ■ indicates a host CPU;
Reference numeral 2a indicates a mask CPU which performs a copy operation as an example of a slave CPU, and reference numeral 2b indicates a scanner CPU which controls an optical system as an example of a slave CPU.

In such a control device, first, when data is input to the host CPU from an operation unit (not shown) such as an operation panel, the program stored in the host CRUI is executed, and the program is transferred to the master CPU 2a via the data bus A. The data is sent to the scanner CPU 2b, and then the mask CPU 2b
The programs stored in U2a and scanner CPU2b are executed to control the mechanical system and optical system, and the master CPU2a and scanner CPU2b also appropriately send responses corresponding to the control of the mechanical system and optical system to the host CPU2. It emits and controls the operating section.

3 is a reset canceling means for canceling the reset state of each CPUI, 2a, 2b and making the GPU 1.2a, 2b into an active state;
It consists of a reset circuit 4 connected to the host CPU, and a delay circuit 5 interposed between the reset circuit 4 and the host CPU. In each embodiment, the delay circuit 5 uses a CR time constant circuit that utilizes charging and discharging of a resistor R3 and a capacitor C2. The delay circuit 5 and the reset circuit 4 are connected to the same power supply Vcc, and after a reset release signal is input to the master CPU 2a and the scanner CPU 2b,
A reset release signal is manually input to the host CPUI.

6 is a power supply voltage monitoring IC for outputting a reset signal when the input power supply voltage drops. Also 7
indicates a buffer buffer amplifier.

The specific circuit operation of the reset release means 3 will be explained below.

First, when the power is turned on, each of the above cpu1.2
a and 2b are maintained in a reset state. At this time, the reset output R of the power supply voltage monitoring IC 6 outputs an "L" level signal, so the master CPU and scanner C
PU2a and PU2b maintain the reset state. Also,
Since the potential at point P of the CR time constant circuit 5 is also maintained at the "L" level through the buffer amplifier 7, the capacitor C2 does not start charging. Therefore, the delay circuit 5 does not operate, and the host CPUI is also kept in a reset state. Next, after the power supply voltage rises and a time period determined by the timing capacitor C1 of the power supply monitoring IC 6 has elapsed, the reset output R changes to the "H" level and is applied to the CPUs 2a, 2b and the delay circuit 5. The master CPU 2a and scanner CPU 2b are released from the reset state by this "H" level signal. On the other hand, the delay circuit 5 starts charging the capacitor C2 when the P point changes to the "H" level through the puffer amplifier 7, and after a predetermined time determined by the time constant of Cm R3 has elapsed, the delay circuit 5 charges the host CPU through the Schmitt trigger circuit 8. Add an “H” level signal to the R terminal of the In this way, the reset state of the host CPU 1 is released.

In this way, according to this embodiment, the reset output R of the reset circuit 4 simultaneously outputs the reset release signal "H" level to the slave CPU, while the host CPU
Since a reset release signal is output to U1 via the delay circuit 5, the reset of the host CPU is always the reset of the slave C.
It will be released after PU2a and PU2b, and all data sent from host CPU1 will be sent to master CPU2a.
The data is received by the scanner CPU 2b, and desired control operations can be performed.

FIG. 2 is a time chart showing the release order of the reset release means. That is, after the power supply voltage is turned on and the power supply rises above the reference level, the delay time by the reset circuit 4 is 1. lapses, the reset output R of the power supply voltage monitoring IC 6 outputs a reset release signal and the master CP
Release the reset state of U2 a and scanner CPU 2b. Thereafter, due to the action of the delay circuit 5, the delay time t
After 2 (tz>t+), a reset release signal is input to the host CPU 1, and the reset state of the host CPU is released.

FIG. 3 shows another embodiment, in which the slave CPUs are a master CPU 2a and a scanner CPU as in the previous embodiment.
2b is used. In this embodiment, the reset canceling means is composed of a plurality of delay circuits 5.
... are connected to each CPUI, 2a, 2b separately, and by selecting a time constant given by the product of the resistance value of the resistor R3 and the capacitance of the capacitor C2 of the delay circuit 5... , master CPU 2a and scanner CPU 2
After the reset release signal is input to b, the above host CP
A reset release signal is input to the UI. In other words, the delay circuit 5 connected to the host CPU
After setting the time constant to be larger than that of the master CPU 2a and scanner CPU 2b, and inputting a reset release signal to the mask CPU 2a and scanner CPU 2b,
A reset release signal is input to the host CPU 1.

According to the above-mentioned configuration, the slave CPUs such as the mask CPU 2a and the scanner CPU 2b always become active, and then the host CPU 1 becomes active, so that the host CPU 1 becomes active.
All data transmitted from the PUI is received by the slave CPU, eliminating any confusion in control operations and achieving the intended purpose.

4 to 6 are flowcharts showing the operating procedure of the control device equipped with the above-mentioned reset release means.

FIG. 4 is a flowchart showing the operating procedure of the host CPU 1. First, when the power is turned on (Sl), the reset state of the host CPU 1 is released after a predetermined period of time has elapsed, as described above. Then internally or externally connected R
AM is cleared and initial settings such as various register settings inside the host CPU I are made (S2). After that,
In order to count the clock pulses of the host CPU, an internal timer set to a predetermined time at the time of initial setting is started (S3). The internal timer is the host CP
U 9 is a timer that sets the time required for one routine of 1. Next, when data is input from the operation unit, a subroutine for controlling the operation unit is executed (S4), and slave CPUs such as the master CPU 2a and the scanner CPU 2b
A subroutine for starting communication with is executed (S5).

When this subroutine process is completed, the routine ends after waiting for the internal timer to end (S6).

Figure 5 shows master CPU2 as an example of slave CPU.
This is a flowchart showing the operation procedure of step a, in which when the power is first turned on (Sll), the reset state of the master CPU 2a is released after a predetermined period of time has elapsed, and the master CPU 2a is reset.
2a becomes active. This reset is canceled before the reset of the (host) CPUI is canceled as described above, and all information from the host (host) CPUI can be taken in. After that, the initial settings such as clearing the RAM and setting various registers are performed in the same manner as the operation of the host CPU 1 (S12), and then a check is made to see if transmission from the host CPU 1 has started (513), until the transmission starts. Wait while the initial settings are completed. When transmission from host CPU 1 starts, an interrupt occurs in this state, and the interrupt data is sent to R of master CPU 2a.
After confirming that it has been stored in AM, the program will proceed again. This interrupt routine is executed while the program of the master CPU 2a is in progress, temporarily interrupting the program as appropriate. Thereafter, the internal timer of the master CPU 2a is set and started (S14), and then a copy operation subroutine is executed (S15). After that, subroutines for handling other processes other than copying operations such as jams and paper jams are executed (516), and when these subroutine processes are completed, the process waits for the internal timer to end and returns to 1.
The routine ends (S17).

Further, FIG. 6 shows a flowchart of the interrupt routine. The interrupt routine is executed by the master CPU 2a.
When the program is being executed, it is interrupted and executed as appropriate.

That is, when an interrupt occurs during a copy operation or other processing by the master CPU 2a, the master CPU temporarily suspends the program currently being executed and executes the interrupt routine. This interrupt routine receives data from the host CPU, stores it in RAM, and at the same time interrupts the mask CPU.
The data stored in the transmission RAM in Za, such as the number of remaining copies of the copying machine, etc., is transmitted to the host CPUI. Then, from the master CPU 2a to the host CPU
The host CPUI controls the operation unit based on the data sent to the host CPU.

In addition, in FIG. 5 and FIG. 6, the case where the master CPU 2a is used as the slave CPU is explained.
Scanner CPU that controls the optical system as a slave CPU
It goes without saying that even when using the optical system, the same operations can be performed by replacing the subroutines for the copying operation and other processing operations with optical system operations.

In this way, the control device of the present invention can control the slave CPU.
Since the reset release signal is input to the host CPU and then the reset release signal is input to the host CPU, there is no possibility of confusion in the control system, and the intended purpose can be achieved.

As detailed above, the present invention includes a host CPU and a plurality of slave CPUs that communicate with the host CPU,
and in a control device equipped with a reset release means for releasing the reset state of the host cPU and the slave CPU, the reset release signal for the host CPU is issued with a delay from the reset/node release signal for the slave CPU. Since the above-mentioned reset canceling means is configured, when the above-mentioned host CPU is in an active state, the slave CPU is also always in an active state, and the above-mentioned slave CPU can receive all the information transmitted from the host CPU. Thus, there is no possibility of confusion caused by a shift in reception timing, and even when the control device is installed in a copying machine, it is possible to perform desired copying operations extremely smoothly.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an overview of one embodiment of the present invention, FIG. 2 is a time chart showing reset release timing, FIG. 3 is a circuit diagram showing an outline of another embodiment of the invention, and FIG. Figure 5 is a flowchart showing the operating procedure of the CPU (host).
The figure is a flowchart showing the operation procedure of the slave CPU,
FIG. 6 is a flowchart of the interrupt routine. ■...Host CPU, 2a-...Master CPU, 2b
. . . Scanner CPU, 3 . . . Reset release means. Figure 2

Claims (3)

[Claims] (1) In a control device comprising a host CPU, a plurality of slave CPUs communicating with the host CPU, and reset release means for releasing the reset state of the host CPU and slave CPUs, the reset release means A control device characterized in that it is configured to issue a reset release signal to a host CPU with a delay from a reset release signal to a slave CPU. (2) A patent characterized in that the reset release means is comprised of one reset circuit connected to the slave CPU and a delay circuit interposed between the reset circuit and the host CPU. A control device according to claim (1). (3) The reset canceling means includes a plurality of delay circuits connected to each CPU separately, and the time constant of the delay circuit connected to the host CPU is set to the slave CPU.
The control device according to claim 1, wherein the time constant is set larger than the time constant of a delay circuit connected to the PU.