JPS63127497A - Shift register - Google Patents

Abstract

PURPOSE:To enable a stable shift operation without a racing, and at the same time, to reduce the number of elements by constituting a storage element by connecting two invertors through a single channel MOS transistor (TR), and further, connecting the elements by using another single channel MOS transistor (TR). CONSTITUTION:At the time of a shift operation, a terminal 11 is given a high level voltage at first, and the terminals 12 and 13 are given with clock pulses phi1 and phi2 respectively, and gates 8 and 9 are made to output these pulses. By such a way, in a section I, all N channels TRs 5-7, 5'-7' are made into OFF, and the gates of CMOS invertors 1-4 are made to store temporarily data stored in the storage elements 14, 15 of Nth stage and (N+1)-th stage. Afterwards, in the section II, because only the TRs 6, 6' to go ON, the invertors 2, 3 to go a connected state, but because the ON-resistance of the TR 6 is small, the data stored in the invertor 2 is transferred earlier to the invertor 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a shift register, in particular, it is capable of stable shifting operation without causing racing;
It also relates to shift registers with a small number of elements.

[Conventional technology]

Conventional static shift registers use devices with a large number of elements, such as D-type flip-flops, as storage elements.

[Problem that the invention seeks to solve]

The conventional shift register described above often uses a D-type flip-flop (hereinafter referred to as D-F/F) as a storage element for storing digital information, but this D-F/F itself has a large number of elements. many more sets,
Attempting to provide a reset function increases the number of elements, which has the drawback of increasing the area, especially when constructed on an integrated circuit.

The object of the present invention is to eliminate the above-mentioned drawbacks with a simple structure,
The objective is to provide a shift register that operates stably.

[Means for solving problems]

In the structure of the shift register of the present invention, the Nth stage storage cell storing one bit of information is arranged between the input of the first inverter and the output of the second inverter, and between the output of the first inverter and the The inputs of the two inverters are connected via first and second single-channel MOS transistors each having a gate input commonly connected to the first control line, and the memory cells of the Nth stage and the N+1th stage are connected to each other. is arranged between the input of the second inverter of the N-th stage and the output of the first inverter in the storage cell arranged in the N+1 stage, and between the output of the second inverter of the N-th stage and the N+1 stage. The inputs of the first inverter in the storage cell are connected through third and fourth single-channel MOS transistors having gate inputs commonly connected to a second control line, and the second and fourth single-channel MOS transistors The MO3 transistor has a smaller on-resistance than the first and third single-channel MoS transistors, and the third and fourth single-channel MoS transistors, the second inverter of the N-stage storage cell, and the N+1-th transistor. The first inverter of the storage cell in the stage temporarily assumes the same configuration as the storage cell during shifting.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a partial circuit diagram of a bidirectional shift register according to an embodiment of the present invention, and FIGS. 2(a) and 2(b) are timing charts during the shift operation of FIG. 1.

In FIG. 1, 1 to 4 are CMOS inverters that constitute storage elements, 5 to 7. 5' to 7' are N channel enhancement MO3) transistors (hereinafter abbreviated as N channel transistors). ), 8 is an N-channel transistor with a smaller on-resistance than
9 is a NAND gate, 10 is an inverter, 11 is a shift 1 to control terminal, 12 to 13 are clock input terminals, and 14.15 is a storage element at the Nth stage and the N+1th stage, respectively.

When performing a shift operation, a high level voltage is applied to the terminal 11, and clock pulses φl and φ2 (not shown in FIG. 2 (a)) are applied to the terminals 12 and 13, respectively. The clock pulses φ1 and C752 are output as shown in FIG. 2(b), respectively.

In section (b) of FIG. 2, all N-channel transistors 5 to 7 and 5' to 7' are turned off, so the data stored in the storage elements 111 and 15 in the N and N+1 stages is transferred to the CM OS inverter. The state remains temporarily stored in the gate capacitors 1 to 4. Since only N-channel transistors 6 and 6' are turned on at the section entrance, CMOS inverter 2.3 is electrically connected, but since the on-resistance of N-channel transistors 1 to 6' is smaller than that of 6', The data stored in the game capacity of 2 is transmitted to the CMOS inverter 3 first, and that data is fed back to the CMOS inverter 2, so the data held by the CMOS inverter 2 is reliably transferred to the CMOS inverter 3. Can be transferred.

In interval ■, all N channels 1 to transistors 5 to 7 and 5' to 7' are turned off, as in interval
The data in the first row remains stored in the gate capacitor of the CMOS inverter 3.

In section V, N-channel transistor 5.5'.

Since 7.7' is turned on, CMOS inverters 1°2, 3, and 4 are electrically connected, but if we focus on the N+l-th stage storage element 15, the on-resistance of 7 is higher than that of 7'. Because the data is small, the data stored in the CMOS inverter 3 is transmitted to the CMOS inverter 4 first, and then fed back to the CMOS inverter 3 again, so the CM
The data held by the OS inverter 3 can be reliably transferred, and as a result, the data stored in the N-th storage element 14 is shifted to the N+1-th storage element 15. .

When a low level voltage is applied to terminal 11, the output of gate 8 becomes low level and the output of gate 9 becomes high level, so N-channel transistor 5.7 remains on, so no shift operation is performed, and each The memory element maintains a stable state of holding data.

〔Effect of the invention〕

As explained above, the present invention configures a memory element by connecting two inverters via a single channel MO3) transistor, and further connects the memory elements with another single channel MO transistor.
By connecting through three transistors, stable shift operation without racing can be performed.
In addition, a shift register with a small number of elements can be constructed.

Additionally, addition of the cell l- and reset l- functions can be realized by adding a few transistors.

[Brief explanation of the drawing]

FIG. 1 is a partial circuit diagram of a bidirectional shift register according to an embodiment of the present invention, and the second Q? l (a) and (b) are timing charts during the shift operation of FIG. 1. 1~4...CMOS inverter, 5~7, 5'~7'
. . . N-channel enhancement MoS transistor, 8 . . . AND gate, 9 . . . NAND gate, 1
0...Inverter, 11...Shift 1~control terminal, 1
2 to 13... Clock input terminal, 14... Nth stage storage element, 15... N+1th stage storage element. to<a)

Claims (1)

[Claims] The Nth stage memory cell that stores one bit of information has a first inverter between the input of the first inverter and the output of the second inverter, and between the output of the first inverter and the input of the second inverter. are connected through first and second single-channel MOS transistors each having a gate input commonly connected to the control line of the N-th stage and the N+1-th stage storage cell. Between the input of the inverter and the output of the first inverter in the memory cell arranged in the N+1 stage, and between the output of the second inverter in the N stage and the input of the first inverter in the memory cell arranged in the N+1 stage are connected via third and fourth single-channel MOS transistors having gate inputs commonly connected to a second control line, and the second and fourth single-channel MOS transistors are connected to the first and third single-channel MOS transistors. the third and fourth single-channel MOS transistors, the second inverters of the N-stage storage cells, and the first inverters of the N+1-th storage cells; A shift register characterized in that it temporarily assumes the same configuration as a storage cell during shifting.