JPS63187352U - - Google Patents

Info

Publication number
JPS63187352U
JPS63187352U JP1987079211U JP7921187U JPS63187352U JP S63187352 U JPS63187352 U JP S63187352U JP 1987079211 U JP1987079211 U JP 1987079211U JP 7921187 U JP7921187 U JP 7921187U JP S63187352 U JPS63187352 U JP S63187352U
Authority
JP
Japan
Prior art keywords
tips
inner leads
lead frame
island
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987079211U
Other languages
English (en)
Other versions
JPH0739243Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987079211U priority Critical patent/JPH0739243Y2/ja
Publication of JPS63187352U publication Critical patent/JPS63187352U/ja
Application granted granted Critical
Publication of JPH0739243Y2 publication Critical patent/JPH0739243Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案によるリードフレームの一実施
例の断面図、第２図は従来構造のリードフレーム
を示す断面図、第３図は本考案によるリードフレ
ームの上面図、第４図は本考案によるリードフレ
ームの第２群インナーリードを立体形成する工程
を示した断面図、第５図は本考案によるリードフ
レームの第２群インナーリードをワイヤボンデイ
ングに際し、裏打ちする方法の一実施例の断面図
である。 １……第２群インナーリード、２……第１群イ
ンナーリード、３……ワイヤ、４……接続電極、
５……半導体素子、６……アイランド、７……イ
ンナーリード、８……リードフレーム。

Claims (1)

    【実用新案登録請求の範囲】
  1. チツプ状の半導体素子を接着固定するアイラン
    ドを中央部に備え、該アイランドに向つて集中し
    相互に平面的に分離されている多数のインナーリ
    ードを有し、前記半導体素子の周縁部に設けられ
    た多数の接続電極と前記インナーリードの先端部
    とをワイヤボンデイングにより接続されるリード
    フレームにおいて、前記インナーリードの先端部
    を一本おきに折り曲げて段差をつけ、隣接するイ
    ンナーリードの先端部を立体的に分離したことを
    特徴とするリードフレーム。
JP1987079211U 1987-05-26 1987-05-26 リードフレーム Expired - Lifetime JPH0739243Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987079211U JPH0739243Y2 (ja) 1987-05-26 1987-05-26 リードフレーム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987079211U JPH0739243Y2 (ja) 1987-05-26 1987-05-26 リードフレーム

Publications (2)

Publication Number Publication Date
JPS63187352U true JPS63187352U (ja) 1988-11-30
JPH0739243Y2 JPH0739243Y2 (ja) 1995-09-06

Family

ID=30928861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987079211U Expired - Lifetime JPH0739243Y2 (ja) 1987-05-26 1987-05-26 リードフレーム

Country Status (1)

Country Link
JP (1) JPH0739243Y2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2007015435A1 (ja) * 2005-08-01 2009-02-19 パナソニック株式会社 半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942427A (ja) * 1972-05-15 1974-04-22
JPS5019404U (ja) * 1973-06-15 1975-03-05
JPS5198963A (ja) * 1975-02-26 1976-08-31

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942427A (ja) * 1972-05-15 1974-04-22
JPS5019404U (ja) * 1973-06-15 1975-03-05
JPS5198963A (ja) * 1975-02-26 1976-08-31

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2007015435A1 (ja) * 2005-08-01 2009-02-19 パナソニック株式会社 半導体装置

Also Published As

Publication number Publication date
JPH0739243Y2 (ja) 1995-09-06

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