JPS6349246B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to correction of 1-bit errors in an arithmetic device that requires writing to correct a 1-bit error in a main memory, particularly in an arithmetic device that has a retry control circuit. This relates to the modified write method.

[Conventional technology and problems]

FIG. 1 is a diagram showing an example of the configuration of an arithmetic unit, FIG. 2 is a diagram explaining a conventional 1-bit error correction write method, and FIG. 3 is a time chart explaining the operation. In the figure, 1 is the main memory (MM;
Main Memory), 2 is the main memory control circuit (MC;
3 is the calculation unit (ALU;
4 is a read register; 5 is an error check correction circuit (ECC);
Error Checking and Correction).

In FIG. 1, a request to use the main memory device 1 from the arithmetic unit 3 to the main memory control circuit 2 is issued as a read request and a write request. In contrast, the main memory control circuit 2 uses the main memory device 1 in read cycles and write cycles.

Conventionally, in an arithmetic device that does not have a retry control circuit as shown in FIG.
The read data is set in the read register, and a 1-bit error (1BER) is detected by the error check correction circuit. If a 1-bit error is detected here, a request is issued for main memory control circuit 2 to use main memory 1 continuously. However, this request is a write request different from a read request at the time of reading, and moreover, it is a write request without write data from the calculation unit 3. the result,
As shown in FIG. 2, corrected data, that is, corrected data output from the read register 4, is passed to the main memory device 1 via an error check correction circuit 5. Therefore, after this write cycle, the main memory device 1 becomes correct data with the 1-bit error corrected. FIG. 3 shows an operation time chart from when a 1-bit error is detected to when a correction is written.

However, in the conventional system as described above, when a 1-bit error occurs infrequently, the processing unit 3
must interrupt the process that should normally be executed next, issue a write request to the main memory control circuit 2, and wait until the main memory control circuit 2 executes a write cycle and writes to correct the 1-bit error. Must be. Since it is necessary to match the main memory control circuit 2 and the arithmetic unit 3, conventionally, the problem has been that it becomes logically complex and prone to logical errors and design errors, which can lead to bugs. It was hot.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
It is an object of the present invention to provide a 1-bit error correction write method that allows a 1-bit error correction write to be performed using simple logic without being conscious of it in an arithmetic unit.

[Structure of the invention]

To this end, the 1-bit error correction write method of the present invention is equipped with a main memory, a main memory control circuit, an arithmetic unit, and a retry control circuit. In an arithmetic device that instructs a main memory control circuit to use the main memory and uses the main memory in read cycles and write cycles, the main memory control circuit performs an error check when reading from the main memory. If a 1-bit error is detected, the retry control circuit is notified of this and the calculation is performed on the condition that the retry control circuit sends a signal indicating that a retry cycle is in progress. The retry control circuit is configured to perform a 1-bit error correction write by converting a read request from the main memory control circuit into a write request and using it as a write cycle. When notified of the occurrence, it is configured to instruct the arithmetic unit to retry and send a signal to the main memory control circuit indicating that a retry cycle is in progress;
The arithmetic unit is characterized in that, when instructed to retry by the retry control circuit, the arithmetic unit is configured to hold a 1-bit error occurrence address and instruct a read request to the main memory control circuit. .

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a diagram showing the system configuration of one embodiment of the present invention, and FIG. 5 is a diagram showing the system configuration of one embodiment of the present invention.
This is a time chart explaining the operation of the error correction light.

In FIG. 4, 1 to 3 indicate those corresponding to FIG. 11, and 6 indicates a retry control circuit (RTY;
Retry). The main memory control circuit 2 includes an arithmetic unit 3
Main memory device 1 by read request and write request from
A request to use the main memory device 1 is issued, and data is read/written to the main memory device 1 in read cycles and write cycles. When reading from the main memory device 1, the main memory control circuit 2 performs an error check on the read data, and if a 1-bit error is detected, it notifies the retry control circuit 6 of the occurrence of a 1-bit error (1BER). . This triggers a retry operation by the retry control circuit 6. The retry control circuit 6 instructs the arithmetic unit 3 to retry using the RTY control signal, and also sends information to the main memory control circuit 2.
The signal during the RTY cycle is set to logic "1". In response to a retry instruction from the retry control circuit 6, the arithmetic unit 3 holds the 1-bit error occurrence address and issues a read request to reuse the address.
On the other hand, the main memory control circuit 2 accepts the read request from the calculation unit 3 on the condition that the signal during the RTY cycle from the retry control circuit 6 is logic "1" (during retry operation). This is converted into a write request and the use of the main storage device 1 is made into a write cycle. In this write cycle, a 1-bit error correction write is performed. In this way, the arithmetic unit 3 issues a read request to the main memory control circuit 2 according to instructions from the retry control circuit 6 when a 1-bit error occurs, so the arithmetic unit 3 does not see it as a write cycle. A 1-bit error correction write can be performed. FIG. 5 shows a time chart illustrating the operation of the 1-bit error correction write described above. In FIG. 5, the calculation retry cycle ends when execution of one instruction is completed.

FIG. 6 is a diagram showing a specific example of the configuration of the arithmetic unit and the main memory control circuit. In FIG. 6, 2 to 6 indicate those corresponding to FIG. 4, 21 is a timing generation circuit, 22, 23, 33 and 34 are latch circuits, 24 is a memory address register, 25
26 to 28 are AND circuits, 29 and 36 are inverting circuits, 31 is an arithmetic control circuit, 32 is an arithmetic circuit, and 35 is an address register.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, when a 1-bit error occurs, a retry operation is activated, and when a read request is issued from the arithmetic unit due to the retry operation, the main memory control circuit By converting the read request into a write request and using it as a write cycle, a 1-bit error correction write is performed, which makes it logically simple and reduces logical errors and design mistakes.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of an arithmetic unit, FIG. 2 is a diagram explaining a conventional 1-bit error correction write method, and FIG. 3 is a time chart explaining the operation.
FIG. 4 is a diagram showing the system configuration of one embodiment of the present invention, and FIG. 5 is a diagram showing the system configuration of one embodiment of the present invention.
FIG. 6 is a time chart illustrating the operation of the error correction write, and is a diagram showing a specific example of the configuration of the arithmetic unit and the main memory control circuit. 1... Main memory device (MM), 2... Main memory control circuit (MC), 3... Arithmetic unit (ALU), 4... Read register, 5... Error check correction circuit (ECC), 6... ...Retry control circuit (RTY). 21...
...timing generation circuit, 22, 23, 33 and 34
... Latch circuit, 24 ... Memory address register, 25 ... Error check correction circuit, 2
6 to 28...AND circuit, 29 and 36...Inversion circuit, 31...Arithmetic control circuit, 32...Arithmetic circuit, 35...Address register.

Claims (1)

[Claims] 1 Comprising a main memory device, a main memory control circuit, an arithmetic unit, and a retry control circuit, the arithmetic unit instructs the main memory control circuit to use the main memory device through read requests and write requests, and In an arithmetic unit that uses the main memory in read cycles and write cycles from the memory control circuit, the main memory control circuit performs an error check when reading from the main memory, and if a 1-bit error is detected, the main memory control circuit performs an error check. , converts the read request from the calculation unit into a write request and writes it, provided that the retry control circuit is notified of this and a signal indicating that the retry cycle is in progress is sent from the retry control circuit.・The retry control circuit is configured to perform a 1-bit error correction write by setting it as a cycle, and when a 1-bit error occurrence notification is received from the main memory control circuit, the retry control circuit instructs the arithmetic unit to retry. The arithmetic unit is configured to send a signal indicating that a retry cycle is in progress to the main memory control circuit along with an instruction, and when the arithmetic unit is instructed to retry from the retry control circuit,
A 1-bit error correction write method characterized in that it is configured to hold a 1-bit error occurrence address and instruct a main memory control circuit to issue a read request.