JPS6349375B2 - - Google Patents

Info

Publication number
JPS6349375B2
JPS6349375B2 JP55005377A JP537780A JPS6349375B2 JP S6349375 B2 JPS6349375 B2 JP S6349375B2 JP 55005377 A JP55005377 A JP 55005377A JP 537780 A JP537780 A JP 537780A JP S6349375 B2 JPS6349375 B2 JP S6349375B2
Authority
JP
Japan
Prior art keywords
bonding
station
frame
position detection
positions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55005377A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56103433A (en
Inventor
Chiaki Iwadare
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP537780A priority Critical patent/JPS56103433A/ja
Publication of JPS56103433A publication Critical patent/JPS56103433A/ja
Publication of JPS6349375B2 publication Critical patent/JPS6349375B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07173—Means for moving chips, wafers or other parts, e.g. conveyor belts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
JP537780A 1980-01-21 1980-01-21 Wire bonding method Granted JPS56103433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP537780A JPS56103433A (en) 1980-01-21 1980-01-21 Wire bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP537780A JPS56103433A (en) 1980-01-21 1980-01-21 Wire bonding method

Publications (2)

Publication Number Publication Date
JPS56103433A JPS56103433A (en) 1981-08-18
JPS6349375B2 true JPS6349375B2 (th) 1988-10-04

Family

ID=11609476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP537780A Granted JPS56103433A (en) 1980-01-21 1980-01-21 Wire bonding method

Country Status (1)

Country Link
JP (1) JPS56103433A (th)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5647697B2 (th) * 1973-06-26 1981-11-11
JPS5160910A (ja) * 1974-11-25 1976-05-27 Hitachi Ltd Riniamoota
JPS54121672A (en) * 1978-03-14 1979-09-20 Nichiden Kikai Kk Wire bonding device
JPS55138246A (en) * 1979-04-13 1980-10-28 Toshiba Corp Manufacture of semicondoctor device

Also Published As

Publication number Publication date
JPS56103433A (en) 1981-08-18

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