JPS634949B2 - - Google Patents

Info

Publication number
JPS634949B2
JPS634949B2 JP57118380A JP11838082A JPS634949B2 JP S634949 B2 JPS634949 B2 JP S634949B2 JP 57118380 A JP57118380 A JP 57118380A JP 11838082 A JP11838082 A JP 11838082A JP S634949 B2 JPS634949 B2 JP S634949B2
Authority
JP
Japan
Prior art keywords
lead pin
lead
layer
insulating layer
multilayer ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57118380A
Other languages
English (en)
Japanese (ja)
Other versions
JPS599951A (ja
Inventor
Kenichi Arakawa
Hideaki Sonoda
Takeyuki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57118380A priority Critical patent/JPS599951A/ja
Publication of JPS599951A publication Critical patent/JPS599951A/ja
Publication of JPS634949B2 publication Critical patent/JPS634949B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP57118380A 1982-07-09 1982-07-09 多層セラミツク基板のリ−ドピン取付構造 Granted JPS599951A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57118380A JPS599951A (ja) 1982-07-09 1982-07-09 多層セラミツク基板のリ−ドピン取付構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57118380A JPS599951A (ja) 1982-07-09 1982-07-09 多層セラミツク基板のリ−ドピン取付構造

Publications (2)

Publication Number Publication Date
JPS599951A JPS599951A (ja) 1984-01-19
JPS634949B2 true JPS634949B2 (2) 1988-02-01

Family

ID=14735263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57118380A Granted JPS599951A (ja) 1982-07-09 1982-07-09 多層セラミツク基板のリ−ドピン取付構造

Country Status (1)

Country Link
JP (1) JPS599951A (2)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59211253A (ja) * 1983-05-17 1984-11-30 Matsushita Electronics Corp 電子部品パツケ−ジ
JPS6424846U (2) * 1987-08-06 1989-02-10
JPH0388354A (ja) * 1989-08-31 1991-04-12 Ibiden Co Ltd 半導体パッケージ
JP3378550B2 (ja) 2000-02-03 2003-02-17 日本特殊陶業株式会社 リードピン付き配線基板

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5457452U (2) * 1977-09-30 1979-04-20
JPS5548700A (en) * 1978-10-04 1980-04-07 Tokyo Shibaura Electric Co Atomic power plant
JPS618608Y2 (2) * 1980-09-26 1986-03-17
JPS5778651U (2) * 1980-10-30 1982-05-15

Also Published As

Publication number Publication date
JPS599951A (ja) 1984-01-19

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