JPS6350049A - Resin sealed type semiconductor device - Google Patents

Resin sealed type semiconductor device

Info

Publication number
JPS6350049A
JPS6350049A JP61194263A JP19426386A JPS6350049A JP S6350049 A JPS6350049 A JP S6350049A JP 61194263 A JP61194263 A JP 61194263A JP 19426386 A JP19426386 A JP 19426386A JP S6350049 A JPS6350049 A JP S6350049A
Authority
JP
Japan
Prior art keywords
semiconductor element
resin
joining
mounting member
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61194263A
Other languages
Japanese (ja)
Other versions
JPH0579173B2 (en
Inventor
Ryuichiro Mori
隆一郎 森
Tatsuhiko Akiyama
龍彦 秋山
Katsuyuki Fukutome
勝幸 福留
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61194263A priority Critical patent/JPS6350049A/en
Priority to US07/085,769 priority patent/US4884124A/en
Publication of JPS6350049A publication Critical patent/JPS6350049A/en
Publication of JPH0579173B2 publication Critical patent/JPH0579173B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the warpage of a semiconductor element with liable to occur joining, and to obviate further warpage after resin seal by cementing the semiconductor element with a joining section having a small area required approximately separated from a non-joining section in a placing member while forming a through-hole to the non-joining section. CONSTITUTION:A semiconductor element 1 is connected to a non-joining section 5b by connecting sections 5c in an area smaller than its own size at the central section of a lower surface, and united with a joining section 5a in a placing member 5 approximately separated from the non-joining section 5b by a joining material 6, and a joining area between the element 1 and the member 5 is relatively kept constant at all times, thus preventing the generation of the warpage of the element 1 with joining. On the other hand, a large number of through-holes 5d are shaped to the non-joining section 5b in the member 5, a sealing resin 2 intrudes into the holes 5d, and adhesion is increased while bonding is strengthened by the entanglement of the resin 2 in the holes 5d, thus also obviating the generation of warpage, after sealing.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、樹脂封止型半導体装置に関し、さらに詳し
くは、半導体素子、その載置部材および封止樹脂相互の
反り防止手段を講じた樹脂封止型半導体装置の改良構造
に係るものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and more particularly, to a resin-sealed semiconductor device, and more particularly, to a resin molded semiconductor device, a mounting member for the semiconductor element, and a resin molded with a means for preventing mutual warpage of the molding resin. This invention relates to an improved structure of a sealed semiconductor device.

〔従来の技術〕[Conventional technology]

従来例によるこの種の樹脂封止型半導体装置の概要構成
断面を第3図および第4図(a)、(b)に示す。
A schematic cross-sectional view of a conventional resin-sealed semiconductor device of this type is shown in FIGS. 3 and 4(a) and 4(b).

すなわち、まず第3図において、符号1は半導体素子、
2は同半導体素子1を封止する封止樹脂であり、また、
3は封1F樹脂内から外部に取出されたそれぞれの導電
部材、4は前記半導体素子1の各端子と各導電部材3と
を電気的に接続する内部リード線、5は前記半導体素子
1を接合材6によって、接合、載置している載置部材で
ある。そしてこ−では、前記各導電部材3および載置部
材5の材料には、通常の場合、銅系合金が用いられる。
That is, first of all, in FIG. 3, reference numeral 1 indicates a semiconductor element;
2 is a sealing resin that seals the semiconductor element 1, and
Reference numeral 3 denotes each conductive member taken out from inside the sealing 1F resin, 4 an internal lead wire that electrically connects each terminal of the semiconductor element 1 and each conductive member 3, and 5 a joint of the semiconductor element 1. This is a mounting member that is joined and mounted by a material 6. In this case, the conductive members 3 and the mounting member 5 are usually made of a copper alloy.

また、第4図(a) 、 (b)は、前記従来例装置で
の半導体素子1と接合材6を介した載置部材5との接合
関係を示す平面図、縦断面図であって、半導体素子lは
、その下面中央部を自身の大きさよりも十分に小さな面
積範囲内で、単一な平板形状をした載置部材5上に、接
合材6を用いて適宜に接合させたものである。
Further, FIGS. 4(a) and 4(b) are a plan view and a longitudinal cross-sectional view showing the bonding relationship between the semiconductor element 1 and the mounting member 5 via the bonding material 6 in the conventional device, The semiconductor element l has its lower surface centrally bonded to a single plate-shaped mounting member 5 using a bonding material 6 within an area sufficiently smaller than the semiconductor element itself. be.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、前記のように構成された従来例による樹
脂封止型半導体装置においては、半導体素子1が大型化
した場合、その載置部材5に対する接合、載置態様のた
めに、安定した接合面積を得ることがはなはだ困難であ
って、接合面積が小さければ、折角、載置させた半導体
素子1が、樹脂封止以前に載置部材5上から脱落する惧
れがあり、また、これとは反対に、接合面積が大きけれ
ば、半導体素子1での基材シリコンの熱膨張係数(Si
 ;約3.5X 10−61/’Cりと、載置部材5の
熱膨張係数(銅系合金;約1.7X 10−61/’C
りとが、相互に大きく異なるために、接合後の温度変化
で、第5図に見られるように、反りを生じて半導体素子
lの破壊を招くことがある。
However, in the conventional resin-sealed semiconductor device configured as described above, when the semiconductor element 1 increases in size, a stable bonding area is required due to the bonding and mounting manner to the mounting member 5. If the bonding area is very difficult to obtain and the bonding area is small, there is a risk that the mounted semiconductor element 1 will fall off from the mounting member 5 before being sealed with the resin. In addition, if the bonding area is large, the thermal expansion coefficient (Si
; about 3.5X 10-61/'C and the thermal expansion coefficient of the mounting member 5 (copper alloy; about 1.7X 10-61/'C
Since the curvatures are greatly different from each other, a temperature change after bonding may cause warping, which may lead to destruction of the semiconductor element 1, as shown in FIG.

また一方、封止樹脂2についても、熱膨張係数(例えば
、エポキシ樹脂:約2〜5×10−51/°C)が半導
体素子1とは大きく異なって、載置部材5に近く、たと
え樹脂」」止具前に半導体素子1に反りを生じていなく
ても、通常の場合、封止樹脂2と半導体素子1間の密着
力に比較して、載置部材5と封止樹脂2間の密着力が弱
いために、先の第3図従来例構成に見られるように、た
とえ素子」−下部分の樹脂厚を相Wに等しくさせてあっ
たとしても(同図中、 t1= t3) 、半導体素子
1と」]止樹脂2とは、封止後の温度変化に伴なって、
同様に反りを生ずることになる。なお、t2は半導体素
子1の厚さである。
On the other hand, the sealing resin 2 also has a thermal expansion coefficient (e.g., epoxy resin: approximately 2 to 5 x 10-51/°C) that is significantly different from that of the semiconductor element 1, and is close to that of the mounting member 5. Even if the semiconductor element 1 is not warped before the fastener, the adhesive strength between the mounting member 5 and the encapsulating resin 2 is usually lower than that between the encapsulating resin 2 and the semiconductor element 1. Due to the weak adhesion, as seen in the prior art configuration in Figure 3, even if the resin thickness at the lower part of the element is made equal to the phase W (t1 = t3 in the figure) , the semiconductor element 1 and the sealing resin 2, as the temperature changes after sealing,
Similarly, warping will occur. Note that t2 is the thickness of the semiconductor element 1.

そこで、第6図に示したように、半導体素子1の上下部
分での封11−樹脂2の厚さを代えることによって(同
図中、 tt<t3) 、半導体素子1の反りを一時的
には抑制し得るものと考えられるが、同時に封止樹脂2
の反りをも解消するのは困難である。
Therefore, as shown in FIG. 6, by changing the thickness of the seal 11 and the resin 2 at the upper and lower parts of the semiconductor element 1 (tt<t3 in the figure), the warpage of the semiconductor element 1 can be temporarily suppressed. It is thought that this can be suppressed, but at the same time, the sealing resin 2
It is also difficult to eliminate warpage.

すなわち、このように従来例による装置構成の場合には
、特に半導体素子が大型化すると、温度変化に伴なう反
りの発生により、この半導体素子自体、あるいは封止樹
脂が破壊されるに至ると云う問題点があった。
In other words, in the case of the conventional device configuration as described above, especially when the semiconductor element becomes large, warping due to temperature changes can lead to destruction of the semiconductor element itself or the sealing resin. There was a problem.

この発明は、従来のこのような問題点を解消するために
なされたもので、その目的とするところは、半導体素子
、その載置部材および封1F樹脂相互の接合に伴なう反
り、ならびに樹脂封止後の半導体素子と封止樹脂の反り
を、それぞれに併せて抑制し得るようにした。この種の
樹脂封止型半導体装置を提供することである。
This invention was made in order to solve these conventional problems, and its purpose is to prevent warping caused by mutual bonding of a semiconductor element, its mounting member, and sealing 1F resin, and to prevent the resin from warping. Warpage of the semiconductor element and the encapsulating resin after encapsulation can be suppressed. An object of the present invention is to provide a resin-sealed semiconductor device of this type.

〔問題点を解決するための手段〕[Means for solving problems]

前記目的を達成するために、この発明に係る樹脂側[ト
型半導体装置は、載置部材に対して、半導体素子の下面
中央部を、自身の大きさよりも十分に小さな面積範囲内
で接合させるための、その接合面積および形状に対応し
た面積、形状の接合部を、適宜に連接部を残して残余の
非接合部から分離させると共に、この非接合部には、表
裏を貫通する複数の貫通孔を穿孔させたものである。
In order to achieve the above object, the resin side [G type semiconductor device according to the present invention has a method in which the lower center portion of the semiconductor element is bonded to the mounting member within an area range sufficiently smaller than the size of the semiconductor element itself. A joint part with an area and shape corresponding to the joint area and shape of the joint part is separated from the remaining non-joint part leaving a suitable joint part, and this non-joint part has multiple through holes penetrating the front and back sides. It has holes drilled in it.

〔作   用〕[For production]

すなわち、この発明においては、半導体素子の下面中央
部を、自身の大きさよりも十分に小さな面積範囲内で接
合させるための、同接合面積、形状に対応した面積、形
状の接合部を、載置部材上に一部連接状態で分離形成さ
せることにより、大型化した半導体素子と載置部材間の
接合面積を一定にでき、また、載置部材の非接合部に複
数の貫通孔を穿孔させ、かつこれらを封止樹脂で一体的
に樹脂封止させることにより、載置部材の接合部を除い
た非接合部と半導体素子間、ならびに各貫通孔内への樹
脂充填をなし得るのである。
In other words, in the present invention, in order to bond the central portion of the lower surface of the semiconductor element within an area range that is sufficiently smaller than the size of the semiconductor element, a bonding portion having an area and shape corresponding to the bonding area and shape is placed. By separately forming parts on the member in a connected state, the bonding area between the enlarged semiconductor element and the mounting member can be made constant, and a plurality of through holes are bored in the non-bonded portion of the mounting member, By integrally sealing these with a sealing resin, resin can be filled between the semiconductor element and the non-bonded portion of the mounting member excluding the bonded portion, as well as into each through-hole.

〔実 施 例〕〔Example〕

以下、この発明に係る樹脂封止型半導体装置の一実施例
につき、第1図および第2図を参照して詳細に説明する
Hereinafter, one embodiment of a resin-sealed semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 and 2.

第1図はこの実施例を適用した樹脂封止型半導体装着の
概要構成を示す縦断面図、第2図は同上載置部材の平面
図であり、これらの実施例各図において、前記第3図従
来例構成と同一符号は同一または相当部分を示している
FIG. 1 is a longitudinal sectional view showing the general structure of a resin-sealed semiconductor mounting to which this embodiment is applied, and FIG. 2 is a plan view of the same mounting member. The same reference numerals as those in the conventional structure in the figure indicate the same or corresponding parts.

この実施例構成においては、前記載置部材5にあって、
前記半導体素子lの下面中央部を、自身の大きさよりも
十分に小さな面積範囲la内で接合させるための、その
接合面積および形状に対応した面積、形状の接合部5a
を、適宜に各連接部5cを一部に残して、残余の非接合
部5bから分離させると共に、この非接合部5bには、
表裏を貫通する複数の貫通孔5dを穿孔させたものであ
る。
In the configuration of this embodiment, the mounting member 5 includes:
A bonding portion 5a having an area and shape corresponding to the bonding area and shape for bonding the central portion of the lower surface of the semiconductor element l within an area range la that is sufficiently smaller than the size of the semiconductor element l.
are separated from the remaining non-joint parts 5b, leaving each connecting part 5c in a part as appropriate, and in this non-joint part 5b,
A plurality of through holes 5d are bored through the front and back sides.

しかして、前記のように形成した接合部利5を用い、そ
の接合部5d上に、半導体素子1の下面中央部での所定
の面積範囲1aを、接合材6により接合、載置させると
きは、半導体素子と載置部材間の接合面積を、例えば、
それぞれの大きさなどに対応して、相対的には常に一定
にできることになり、これによって接合に伴なう半導体
素子の反りを効果的に抑制し得るのである。
Therefore, when using the bonding portion 5 formed as described above and bonding and placing a predetermined area range 1a at the center of the lower surface of the semiconductor element 1 on the bonding portion 5d using the bonding material 6, , the bonding area between the semiconductor element and the mounting member is, for example,
Corresponding to each size, etc., it can be kept relatively constant at all times, and thereby it is possible to effectively suppress the warpage of the semiconductor element that accompanies bonding.

また、前記半導体素子1と載置部材5とを、このように
接合、載置させた状態で、これらの両者を、封止樹脂2
により所定通りに樹脂封止させるときは、載置部材5の
接合部5aを除いた残余の非接合部5bと半導体素子1
間、ならびに各貫通孔5d内に十分な樹脂充填をなし得
ることになり、特にそれぞれの貫通孔5d部分では、封
止樹脂2の絡み付きによって、強固な結合がなされるも
ので、このため機械的に載置部材5の各部と封止樹脂2
との密着力を十分に増加でき、同様に反りに対する抑制
効果を十分に発揮し得るのである。
Further, in the state where the semiconductor element 1 and the mounting member 5 are bonded and mounted in this manner, both of them are sealed with a sealing resin 2.
When resin sealing is performed as specified by
This allows sufficient resin to be filled between the holes and in each of the through holes 5d, and in particular, in the portions of each through hole 5d, a strong bond is formed by the entanglement of the sealing resin 2. Therefore, mechanical Each part of the mounting member 5 and the sealing resin 2
This can sufficiently increase the adhesion force with the material, and can also sufficiently suppress warpage.

そしてまた、一般に前記載置部材5が銅系合金材料であ
って、封止樹脂2との熱膨張係数が近似していることか
ら、前記半導体素子1での上下部分のvA脂厚がはぐ等
しく(第1図中、tt=t3)なるようにするときは、
同各部での熱膨張を均衡させ得て、樹脂封止後における
これらの半導体素子1と封止樹脂2との相互の反りをも
抑制できることになる。
Furthermore, since the mounting member 5 is generally made of a copper-based alloy material and has a thermal expansion coefficient similar to that of the sealing resin 2, the vA thickness of the upper and lower portions of the semiconductor element 1 is approximately equal. (tt=t3 in Figure 1),
Thermal expansion in each part can be balanced, and mutual warpage between the semiconductor element 1 and the sealing resin 2 after resin sealing can be suppressed.

すなわち、このようにして、この実施例構成の場合には
、実質的に半導体素子1.その載置部材5および」4止
樹脂2の各相互間での反りを、良好かつ効果的に防止で
きるのである。
That is, in this embodiment configuration, substantially the semiconductor device 1. It is possible to effectively and effectively prevent warping between the mounting member 5 and the "4" stopper resin 2.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、この発明によれば、半導体素子の
下面中央部を、載置部材−Lに接合材により接合、載置
させ、これらの半導体素子、および載置部材のそれぞれ
を樹脂封止して構成する樹脂封+I−,型半導体装置に
おいて、半導体素子の下面中央部を、自身の大きさより
も十分に小さな面積範囲内で接合させるための、同接合
面積、形状に対応した面積、形状の接合部を、載置部材
上に一部連接状態で分離形成させるようにしたので、半
導体素子と載置部材間の接合面積を、相対的に常に一定
にできて、接合に伴なう半導体素子の反りを効果的に抑
制させることができる。
As described in detail above, according to the present invention, the central part of the lower surface of the semiconductor element is bonded and placed on the mounting member-L using a bonding material, and the semiconductor element and the mounting member are each sealed with resin. In a resin-sealed +I-, type semiconductor device, in order to bond the center part of the lower surface of the semiconductor element within an area range sufficiently smaller than the size of the semiconductor element, an area corresponding to the same bonding area and shape, Since the shaped joints are formed separately on the mounting member in a partially connected state, the joint area between the semiconductor element and the mounting member can be kept relatively constant at all times, and the Warpage of the semiconductor element can be effectively suppressed.

また、載置部材の非接合部には、複数の貫通孔を穿孔さ
せた〜めに、これらの各貫通孔の存在により、樹脂封止
時での溶融樹脂の流れが円滑化され、その結果、載置部
材の接合部を除いた非接合部と半導体素子間の隙間、そ
れに各貫通孔内への樹脂充填が完全かつ確実になされて
、密着力の向上を図り得ると共に、特にそれぞれの貫通
孔部分では、封止樹脂の絡み付きにより、強固な結合が
なされて、各部材相互の一体化、ひいては反り防止を容
易に達成でき、しかも構造的にも極めて簡単で、容易か
つ安価に実施し得るなどの優れた特長を有するものであ
る。
In addition, since multiple through holes are drilled in the non-bonded part of the mounting member, the presence of each of these through holes facilitates the flow of molten resin during resin sealing, and as a result, , the gap between the non-bonded part of the mounting member excluding the bonded part and the semiconductor element, and the resin filling into each through hole are completely and reliably filled, and it is possible to improve the adhesion strength, and especially to improve the adhesive strength of each through hole. In the hole part, a strong bond is formed by entangling the sealing resin, making it easy to integrate each member with each other and prevent warping. Moreover, it is extremely simple in structure and can be implemented easily and inexpensively. It has excellent features such as:

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明に係る樹脂封止型半導体装置の一実施
例による概要構成を示す縦断面図、第2図は同上載置部
材の平面図であり、また第3図は従来例による同上半導
体装置の概要構成を示す縦断面図、第4図(a) 、 
(b)は同上半導体素子と載置部材との接合関係を示す
平面図、縦断面図、第5図および第6図は同上従来例で
の反りの状態およびその対応構造をそれぞれに示す断面
説明図である。 1・・・・半導体素子、1a・・・・接合面積範囲、2
・・・・封止樹脂、3・・・・導電部材、4・・・・内
部リード線、5・・・・載置部材、5a・・・・接合部
、5b・・・・非接合部、5c・・・・連接部、5d・
・・・貫通孔、6・・・・接合材。 代理人  大  岩  増  雄 第1図 第2図 第3図 第4図
FIG. 1 is a vertical cross-sectional view showing the general configuration of an embodiment of a resin-sealed semiconductor device according to the present invention, FIG. 2 is a plan view of a mounting member of the same, and FIG. 3 is a conventional example of the same. A vertical cross-sectional view showing the general configuration of a semiconductor device, FIG. 4(a),
(b) is a plan view and a vertical sectional view showing the bonding relationship between the semiconductor element and the mounting member, and FIGS. 5 and 6 are cross-sectional explanations showing the state of warpage and the corresponding structure in the conventional example as above, respectively. It is a diagram. 1... Semiconductor element, 1a... Junction area range, 2
... Sealing resin, 3... Conductive member, 4... Internal lead wire, 5... Placement member, 5a... Joint part, 5b... Non-joining part. , 5c...Connection part, 5d.
...Through hole, 6...Joining material. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] (1)少なくとも半導体素子の下面中央部を、載置部材
上に接合材により接合、載置させ、これらの半導体素子
、および載置部材のそれぞれを樹脂封止して構成する樹
脂封止型半導体装置において、前記載置部材に対して、
前記半導体素子の下面中央部を、自身の大きさよりも小
さな面積範囲内で接合させるための、その接合面積、形
状に対応した面積、形状の接合部を、適宜に連接部を残
して残余の非接合部から分離させると共に、この非接合
部には、表裏を貫通する複数の貫通孔を穿孔させたこと
を特徴とする樹脂封止型半導体装置。
(1) A resin-sealed semiconductor in which at least the central part of the lower surface of a semiconductor element is bonded and placed on a mounting member using a bonding material, and the semiconductor element and the mounting member are each sealed with resin. In the device, for the mounting member,
In order to bond the central part of the lower surface of the semiconductor element within an area smaller than the semiconductor element itself, a bonding part with an area and shape corresponding to the bonding area and shape is created by leaving a connecting part as appropriate and removing the remaining non-contact part. 1. A resin-sealed semiconductor device characterized in that the non-bonded part is separated from the bonded part and has a plurality of through holes penetrating the front and back sides thereof.
JP61194263A 1986-08-19 1986-08-19 Resin sealed type semiconductor device Granted JPS6350049A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP61194263A JPS6350049A (en) 1986-08-19 1986-08-19 Resin sealed type semiconductor device
US07/085,769 US4884124A (en) 1986-08-19 1987-08-17 Resin-encapsulated semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61194263A JPS6350049A (en) 1986-08-19 1986-08-19 Resin sealed type semiconductor device

Publications (2)

Publication Number Publication Date
JPS6350049A true JPS6350049A (en) 1988-03-02
JPH0579173B2 JPH0579173B2 (en) 1993-11-01

Family

ID=16321718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61194263A Granted JPS6350049A (en) 1986-08-19 1986-08-19 Resin sealed type semiconductor device

Country Status (1)

Country Link
JP (1) JPS6350049A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19639181A1 (en) * 1996-09-24 1998-04-02 Siemens Ag Lead frame for a microelectronic component
US6265770B1 (en) * 1998-03-24 2001-07-24 Seiko Epson Corporation Mounting structure of semiconductor chip, liquid crystal device, and electronic equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5295173A (en) * 1976-02-06 1977-08-10 Hitachi Ltd Lead frame
JPS554983A (en) * 1978-06-27 1980-01-14 Nec Kyushu Ltd Lead frame for semiconductor device
JPS56161356U (en) * 1980-04-28 1981-12-01

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5295173A (en) * 1976-02-06 1977-08-10 Hitachi Ltd Lead frame
JPS554983A (en) * 1978-06-27 1980-01-14 Nec Kyushu Ltd Lead frame for semiconductor device
JPS56161356U (en) * 1980-04-28 1981-12-01

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19639181A1 (en) * 1996-09-24 1998-04-02 Siemens Ag Lead frame for a microelectronic component
US6265770B1 (en) * 1998-03-24 2001-07-24 Seiko Epson Corporation Mounting structure of semiconductor chip, liquid crystal device, and electronic equipment

Also Published As

Publication number Publication date
JPH0579173B2 (en) 1993-11-01

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