JPS6355449U - - Google Patents

Info

Publication number
JPS6355449U
JPS6355449U JP1986147950U JP14795086U JPS6355449U JP S6355449 U JPS6355449 U JP S6355449U JP 1986147950 U JP1986147950 U JP 1986147950U JP 14795086 U JP14795086 U JP 14795086U JP S6355449 U JPS6355449 U JP S6355449U
Authority
JP
Japan
Prior art keywords
bonding
package
pin terminal
positions
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986147950U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986147950U priority Critical patent/JPS6355449U/ja
Publication of JPS6355449U publication Critical patent/JPS6355449U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5475—Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案のＩＣパツケージの一実施例の
縦断面図、第２図は本考案のＩＣパツケージの一
実施例の平面図、第３図は第１，２図の実施例の
ＩＣパツケージにおけるボンデイングワイヤの長
さの選択性を示す説明図、第４図は第１，２図の
実施例のＩＣパツケージのスクライブ線とボンデ
イングワイヤとの角度の選択性を示す説明図、第
５図は第１，２図の実施例のボンデイングステツ
チを有するＩＣパツケージの２点ボンデイングを
示す説明図、第６図は従来のＩＣパツケージにお
ける２点ボンデイングを示す説明図である。 １……ピン端子、２，３……ボンデイングステ
ツチ、４……ＩＣチツプ、５……ボンデイングワ
イヤ、６……ＩＣパツケージ、７……ボンデイン
グパツト。

Claims (1)

    【実用新案登録請求の範囲】
  1. ＩＣパツケージにおいて、各ピン端子に対し内
    部配線パターンを経由して互いに高さおよび位置
    の異る２個のボンデイングステツチを設けてなる
    ことを特徴とするＩＣパツケージ。
JP1986147950U 1986-09-26 1986-09-26 Pending JPS6355449U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986147950U JPS6355449U (ja) 1986-09-26 1986-09-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986147950U JPS6355449U (ja) 1986-09-26 1986-09-26

Publications (1)

Publication Number Publication Date
JPS6355449U true JPS6355449U (ja) 1988-04-13

Family

ID=31061780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986147950U Pending JPS6355449U (ja) 1986-09-26 1986-09-26

Country Status (1)

Country Link
JP (1) JPS6355449U (ja)

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