JPH01171047U - - Google Patents

Info

Publication number
JPH01171047U
JPH01171047U JP1988067387U JP6738788U JPH01171047U JP H01171047 U JPH01171047 U JP H01171047U JP 1988067387 U JP1988067387 U JP 1988067387U JP 6738788 U JP6738788 U JP 6738788U JP H01171047 U JPH01171047 U JP H01171047U
Authority
JP
Japan
Prior art keywords
shape
semiconductor device
lead frame
stitch
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988067387U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988067387U priority Critical patent/JPH01171047U/ja
Publication of JPH01171047U publication Critical patent/JPH01171047U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図はこの発明の一実施例による半導体装置
用リードフレームを示す平面図、第２図および第
３図は第１図のリードピンの先端形状の部分拡大
図、第４図は従来の半導体装置用リードフレーム
を示す平面図、第５図は従来のワイヤボンド工程
での拡大断面図である。 図において、１はリードフレーム、２はダイパ
ツド、３は中吊りピン、４はパツド、５はステツ
チ、６はワイヤ、７はＩＣチツプを示す。なお、
図中、同一符号は同一、又は相当部分を示す。

Claims (1)

    【実用新案登録請求の範囲】
  1. ワイヤボンド工程においてステツチボンドをす
    る半導体装置用リードフレームの先端形状をパツ
    ドとステツチ位置を結ぶ直線と平行となる形状、
    またはこの形状より外側方向にリード幅が大きく
    なる形状を有することを特徴とする半導体装置用
    リードフレーム。
JP1988067387U 1988-05-20 1988-05-20 Pending JPH01171047U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988067387U JPH01171047U (ja) 1988-05-20 1988-05-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988067387U JPH01171047U (ja) 1988-05-20 1988-05-20

Publications (1)

Publication Number Publication Date
JPH01171047U true JPH01171047U (ja) 1989-12-04

Family

ID=31292759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988067387U Pending JPH01171047U (ja) 1988-05-20 1988-05-20

Country Status (1)

Country Link
JP (1) JPH01171047U (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8868829B2 (en) 2006-07-31 2014-10-21 Google Inc. Memory circuit system and method
US8972673B2 (en) 2006-07-31 2015-03-03 Google Inc. Power management of memory circuits by virtual memory simulation
US8977806B1 (en) 2006-10-05 2015-03-10 Google Inc. Hybrid memory module
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US8868829B2 (en) 2006-07-31 2014-10-21 Google Inc. Memory circuit system and method
US8972673B2 (en) 2006-07-31 2015-03-03 Google Inc. Power management of memory circuits by virtual memory simulation
US8977806B1 (en) 2006-10-05 2015-03-10 Google Inc. Hybrid memory module

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