JPS635788B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a completely distributed common bus control system for a multi-purpose computer system that prevents bus use requests of modules with low priority from being extremely postponed.

Conventionally, there have been various types of control devices when a complex system is connected to a common bus. A method in which a control section is provided that separately determines and controls the priority order of use for the entire complex system is different from a completely distributed control method, in that even if a failure in the control system occurs locally, the entire system is affected. Furthermore, even with a completely distributed control method, in conventional methods, when bus usage requests from multiple modules conflict, the usage order is always determined according to the priority unique to each module. Other problems have arisen in that requests for such services sometimes have to wait for a very long time. In order to solve this problem, a bus usage reservation registration system has been used in the past, but in the conventional method, modules are connected in series by mask lines, and access by other modules with lower priority is prohibited. Because it is a system that uses a multi-module system, it is not completely distributed control, and there is a high possibility that a failure in one module will affect other modules. In addition, with a completely distributed control method, when the bus becomes free, the module that has requested to use the bus immediately starts transmitting without being aware of other modules, and if it collides with another module, it is detected by the data error detection function and a random number is sent. A method of retransmitting after a time determined by is also known, but it has drawbacks such as complicated hardware and software and low bus usage efficiency.

The present invention does not have the problems of the conventional method,
The purpose of the present invention is to provide a common bus control method for a compound computer system that is completely distributed and does not require modules with low priority to wait for an extremely long time.

In order to achieve the above object, in the present invention,
A module that is equipped with a bus registration line as a common bus will send a signal indicating bus usage reservation to the bus registration line only if there is no signal from another module on the bus registration line. During this time, other modules were prohibited from registering new bus reservations. Even if a bus usage request occurs to multiple modules while the bus is in use, the registration of bus usage reservations for these multiple modules is prohibited as described above, but as soon as the bus becomes vacant, the bus usage reservation registration is At some point, the multiple modules that were waiting and prohibited from using the bus sent signals to the bus registration line, and all of them entered the bus reservation state. It was decided that the buses would be used sequentially among the plurality of modules that were in the bus use reservation state according to the priority order unique to each module. In this way, a module that enters the bus reservation state will not be able to register for the bus even if a module with a higher priority than that module receives a request to use the bus, until that module finishes using the bus. By continuing to send signals to the line, registering new modules to use the bus is prohibited, so the bus can be used without interference. Therefore, unlike in the case of the fixed priority system, modules with low priority are not forced to wait for an extremely long time.

FIG. 1 is an explanatory diagram of the operation of the present invention. At the top, the time when a bus use request is generated is indicated by an arrow, and the numbers indicate the module number and priority, and the larger the number of modules, the higher the priority. Below that, the time course of the common bus use of each module is shown, where A is for the method of the present invention and B is for the fixed priority method. Since the bus usage request for module #4 occurred when it was in an empty state, the bus usage was immediately assigned to both A and B. There is a difference. In case A of the present invention, bus usage requests for modules #3 and #5 that occur while module #4 is using the bus are both registered when module #4 ends using the bus, and are sent to modules #5, #5 according to priority. Bus usage requests for modules #8, #1, and #6 that occur while modules #5 and #3 are using the bus are registered when module #3 ends using the bus, and module #3 is used in this order. The buses are used in the order of 8, #6, and #1. On the other hand, in the case of fixed priority B, when a module finishes using the bus,
Each time, the module with the highest rank among the modules waiting to use the bus uses the bus.

FIG. 2 is a diagram showing a module according to an embodiment of the present invention, in which bus 17 is a system bus consisting of all buses related to data transfer between processing units 1, namely address lines, data lines, and control lines, and bus 18 is a system bus consisting of address lines, data lines, and control lines. The bus busy line that indicates whether the system bus is in use or not, bus 19, is the bus registration line.
The two components constitute a common bus, and the illustrated portions other than the common bus constitute one module. The outputs 6 and 8 of the control unit 5 and the output of the decoder 16 for converting n into 2 ⁿ are wired-ORed with other modules, respectively. As shown in FIG. 3, the control unit 5 has six statuses S ₀ , S _{1 .} . . S ₅ . Although not shown in FIG. 3, when a reset signal 21 is applied to the control section 5, the control section 5 returns to the initial state _S0 regardless of the state at that time. When processing unit 1 requests the use of a common bus to exchange data with other modules (processing units, shared memory, etc.) and turns on bus request line 2, the status shifts to _S1 . The control unit 5 checks the bus registration line 7, and if it is off, the status
Move on to _S2 . At this time, the bus registration line 6 is turned on. Next, the bus busy line 9 is checked, and if it is off, the status moves to _S3 and the bus busy line 8 is turned on. Also, at this time, the priority unique to this module is output to the priority line 12. This value is n
is decoded by a decoder 16 that ^converts For example, if priority n=3 and the decoded priority value is 1000 in binary, negative logic
11110111 is output to the output line 15. Note that the priority number also serves as a number indicating a module, and the larger the number, the higher the priority.
The output line 15 does not need to be provided independently, and can be shared with the bus used by the processing unit to send and receive data. At this time, at the same time, for example, priority level n=2
When the module ( ²ⁿ value is 100 in binary) is operating (priority transmission), the input of the priority encoder 14 becomes 11110011 by wire-ORing 11110111 and 11111011 with negative logic. The input to the encoder 14 is inverted to become 00001100, the most significant digit of which is converted from 2 ⁿ to n, and n=3 is output to the output line 11 of the encoder. That is, the highest priority value of the competing modules is output to the output line 11. Comparator 10
turns on the priority matching line 13 when the output values of the output lines 11 and 12 match.
If they do not match, the control unit status returns to _S2 ,
Priority output ends. If they match, the process moves to status _S5 , the priority output ends, and the bus use permission line 3 is turned on. The processing unit uses the bus 17 via line 20 and turns on the bus end line 4 when it is finished. As a result, the status of the control section 5 returns to _S0 . The output period of the output line of the control unit ₅ is also shown on the left side of FIG. At the end, the bus busy-on period also ends, but as described above, the bus registration on state continues until the module is turned on at the end of bus use. The bus busy-on output period may be limited to status _S5 . If two or more modules move to status S ₂ at the same time, they are allowed to use the bus in order from the one with the highest priority, and if new requests occur during that time, even if they are from the module with the highest priority, they are As mentioned above, the terminal must remain in status _S1 and wait. Note that when the number of modules is greater than 2 ⁿ , this can be handled by dividing and outputting the priority into two or more. At this time, statuses S ₃ and S ₄ consist of two or more pairs, and only the one with the highest priority at each stage is
Proceed to the next stake S ₅ , all others return to status S ₂ .

As explained above, according to the present invention, there is no need for modules with low priority to wait for an extremely long time, and even if a failure occurs somewhere, the effect remains local and the failure does not spread over a wide area of the system. , and other effects can be obtained.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the operation of the present invention, FIG. 2 is a diagram showing a module according to an embodiment of the present invention, and FIG. 3 is a diagram showing the status of the module control section and its output period according to the present invention. 1...processing unit, 5...control unit,
10... Comparator, 14... Priority encoder, 16... Decoder, 17... System bus, 18... Bus busy line, 19... Bus registration line.

Claims (1)

[Claims] 1. In a compound computer system consisting of a plurality of modules connected to a common bus, the common bus consists of a system bus, a busy line, and a bus registration line, and each module connects the bus registration line to the bus registration line when a request to use the bus occurs. On condition that there is no bus use request signal from another module, a bus use request signal is output to the corresponding bus registration line, and if the busy line is on, it waits until it becomes off, and then the bus is turned off. In this case, an on signal is output to the busy line, and a priority signal unique to the own module is sent to the system bus, and based on the state of the signal appearing on the system bus, the competing module has a higher priority than the own module. The presence or absence of a module is determined, and the module determined to be at the highest level executes processing using the above-mentioned common bus and stops outputting the above-mentioned bus use request signal and busy signal at the end of processing. A common bus control method for a compound computer system, characterized in that each module that has been determined to have the same status waits until the busy line is turned off again and then repeats the operation for determining the priority order.