JPS6399580A - Tunnel injection control semiconductor device - Google Patents

Tunnel injection control semiconductor device

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Publication number
JPS6399580A
JPS6399580A JP62250183A JP25018387A JPS6399580A JP S6399580 A JPS6399580 A JP S6399580A JP 62250183 A JP62250183 A JP 62250183A JP 25018387 A JP25018387 A JP 25018387A JP S6399580 A JPS6399580 A JP S6399580A
Authority
JP
Japan
Prior art keywords
region
gate
source
tunnel
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62250183A
Other languages
Japanese (ja)
Other versions
JPH046111B2 (en
Inventor
Junichi Nishizawa
潤一 西澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Research Foundation
Original Assignee
Semiconductor Research Foundation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Research Foundation filed Critical Semiconductor Research Foundation
Priority to JP62250183A priority Critical patent/JPS6399580A/en
Publication of JPS6399580A publication Critical patent/JPS6399580A/en
Publication of JPH046111B2 publication Critical patent/JPH046111B2/ja
Granted legal-status Critical Current

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  • Bipolar Transistors (AREA)
  • Non-Volatile Memory (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To eliminate the carrier storing effect almost completely and to obtain a semiconductor device operating at an extremely high speed, by tunnel implanting an impurity from at least part of a source and a channel to provide a gate region in contact with the channel, so that control is performed by the gate region. CONSTITUTION:A p<++> region 11 serves as a source region and an n<+> region 14 as a drain region. Reference marks 15 and 15' indicate gate electrodes. Potential distribution of an n-type region 13 is regulated at that of the n<+> region providing a current path through an insulation film 16. The impurity concentrations of the n<+>-type region 12 and the n-type region 13 are made higher, the shorter the distance between gates is or the shorter the distance between gate and drain is. A gate voltage is applied to the n<+> region more effectively, the thinner the insulation film 16 contacted with the n<+> 12 is. In order to supply more tunnel current, it is better that the n<+> region 12 has a higher concentration of impurity and a smaller thickness.

Description

【発明の詳細な説明】 本発明は、半導体デバイスの微細化高速化の極限にある
デバイスであり、制御電極の静電誘導効果によりソース
前面の電位分布を制御しトンネル注入電流を制御する半
導体デバイスに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention is a device that is at the ultimate limit of miniaturization and speeding up of semiconductor devices, and is a semiconductor device that controls the potential distribution in front of the source by the electrostatic induction effect of the control electrode and controls the tunnel injection current. Regarding.

従来、キA・リアの注入量制御を動作原理と覆る1−ラ
ンジスタには、バイポーラ1−ランジスタ(以下B P
王ど称づ)及び静電誘II +−ランジスタ〈以下SI
Tと称す)がある。Bl)Tでは、制御電極であるベー
ス電極の電圧でベースの電位をベース抵抗を介して制御
し、エミッタから流れ込む少数キャリアの量を制御して
いる。一方、SITでは、電流の流れるチャンネル領域
は殆んともしくは完全に空乏化し、制御電極であるグー
1へ電極の電圧でチャンネル領域を容量結合で制御し、
ソース領域からのキャリアの注入量を制御している。い
ずれのトランジスタにおいても、電位障壁を熱■ネルギ
により越えて流れる電流を制御しているわけである。従
って、それほど多くはないが、電位障壁とソースもしく
は丁ミッタの間に、キャリノアの蓄積効果が存在し、超
高速動作時の速度制限の一つの要因になっていた。
Conventionally, bipolar 1-transistors (hereinafter referred to as B P
) and electrostatic dielectric II +- transistor (hereinafter referred to as SI)
(referred to as T). In Bl)T, the potential of the base is controlled by the voltage of the base electrode, which is a control electrode, via the base resistor, and the amount of minority carriers flowing from the emitter is controlled. On the other hand, in SIT, the channel region through which current flows is almost or completely depleted, and the channel region is controlled by capacitive coupling to the control electrode Goo 1 using the electrode voltage.
The amount of carrier injection from the source region is controlled. In any transistor, the current flowing across the potential barrier is controlled by thermal energy. Therefore, although not so much, there is a carrier accumulation effect between the potential barrier and the source or emitter, which is one of the factors that limits the speed during ultra-high-speed operation.

本発明の目的は、こうしたキャリアの蓄積効果を殆んど
完全に除去し、極めて高速で動作Jる半導体デバイスを
提供づることである。
An object of the present invention is to provide a semiconductor device that almost completely eliminates such carrier accumulation effects and operates at extremely high speed.

以下図面を参照しながら本発明の詳細な説明づる3゜ まず、p + n接合ダイオ〜ドに逆バイアスを加えた
場合の1〜ンネル電流について)」(べる。直接)テ移
型トンネル電流密度の式は次式でIjえられる、。
The following is a detailed explanation of the present invention with reference to the drawings. 3. First, regarding the tunnel current when reverse bias is applied to a p + n junction diode (direct) transfer type tunnel current The formula for the density is given by the following formula.

ただし、2:単位電荷、nlx :右効質吊、1)=2
π毛ニブランク定数、ε督:バンドキャップ、■oL:
印加電圧、及びFはll”l’l接合の最大で与えられ
る。ここで、ND:n領域の不純物密m、ε5:半導体
の誘電率、Vb;:p”n接合の拡散電位である。式く
1)、(2)で与えられるp”n接合の逆方向1−ンネ
ル電流密度の逆り向印加電圧ユ依存性を第1図に承り。
However, 2: unit charge, nlx: right effect suspension, 1) = 2
π-blank constant, ε: band cap, ■oL:
The applied voltage and F are given at the maximum of the ll"l'l junction. Here, ND: impurity density m of the n region, ε5: dielectric constant of the semiconductor, Vb;: diffusion potential of the p"n junction. Figure 1 shows the dependence of the reverse channel current density of the p''n junction on the reverse applied voltage given by equations 1) and (2).

第1図は、半導体材料をGaAsとして計紳した結果で
ある。従って、ε、=1.43eV、ε、=10.9ε
。である。ε。は真空の誘電率である。
FIG. 1 shows the results obtained by using GaAs as the semiconductor material. Therefore, ε,=1.43eV, ε,=10.9ε
. It is. ε. is the dielectric constant of vacuum.

m * −(t、−± 1.、−s me、   rne+h であり、III b”  = 0 、068 m OX
III ah” = 0.121110である。moは
自由電子の質量である。第1図には、電流密度が実線で
、電界強度が点線で示されている。Nは、n領域の不純
物密度である。Nが大ぎくなるに゛っれ空乏層幅が狭く
なり、電界「が大きくなるから、電流密度は大きくなる
。例えば、N=3X1Q18Ql−3では、電圧1Vで
3 X 10sA/cm2(1)電流密度が得られる。
m * −(t, −± 1., −s me, rne+h, and III b” = 0, 068 m OX
III ah" = 0.121110. mo is the mass of free electrons. In Figure 1, the current density is shown as a solid line and the electric field strength is shown as a dotted line. N is the impurity density in the n region. As N becomes larger, the depletion layer width becomes narrower and the electric field becomes larger, so the current density becomes larger.For example, when N=3X1Q18Ql-3, at a voltage of 1V, 3 ) current density is obtained.

ここで計算したように直接遷移でトンネル注入が生起す
る半導体材料の方が間接遷移のものよりも低い電圧でト
ンネル注入を効率よく起こすことができる。
As calculated here, semiconductor materials in which tunnel injection occurs through direct transition can cause tunnel injection more efficiently at a lower voltage than those with indirect transition.

第1図のように157られるトンネル電流を、制御電極
であるグー1−とドレイン電圧で制御する構造にしたも
のが本発明の半導体デバイスである。
The semiconductor device of the present invention has a structure in which the tunnel current 157 as shown in FIG. 1 is controlled by the control electrode G1- and the drain voltage.

第2図に本発明の1ヘランジスタの動作を説明(るため
の断面構造を示す。p1+領域11はソース領域、n+
領域14はドレイン領域、15及び15′はゲート電極
であり、絶縁膜16を介して電流通路となるn+領領域
、n領域13の電位分布を制御している。各領域の不純
物密度は、グーl−・ゲート間隔にJ、るが、p++領
域11:5x10 −1Xl0”cm−3、n+12+
5xlO−1xl0  cm  、n13:lX10 
  〜 lX10    Cm   、 n    1
4:1X10′8〜5×1020clTl−3である。
FIG. 2 shows a cross-sectional structure for explaining the operation of the one-herald transistor of the present invention. The p1+ region 11 is a source region, and the n+
A region 14 is a drain region, and 15 and 15' are gate electrodes, which control the potential distribution of the n+ region and the n region 13, which serve as current paths, via an insulating film 16. The impurity density of each region is J, depending on the gate spacing, but the p++ region 11: 5 x 10 -1
5xlO-1xl0 cm, n13:lX10
~ lX10 Cm, n1
4:1×10'8 to 5×1020 clTl-3.

n+12.1]13各領域の不純物密度は、グー1−・
グー1ル間隔が短し舅よど、またソース・ドレイン間隔
が短い稈高くする。ゲート・ゲート間隔は例えば2μm
以上から1000A程麿、ソース・ドレイン間隔は、1
000Aから2〜3μm程度である。n4“12に接す
る絶縁膜16は薄い程、有効にゲート電圧がn+12領
域に加わる3、トレインに正電圧を印加した状態のソー
ス・ドレイン方向の電位分布を第3図に示(。<a>は
グ−トにも正電圧を加えて導通状態になったときの電位
分布、(b )はゲートを零電位(ソースも同電位)と
したときの遮断状態での電位分布である。(a)では、
ゲートに正電圧が加わっているためソース前面の電位の
勾配がより急峻になっており、(b)ではゲート電圧に
より、よりゆるやかになっている。この勾配から決まる
電界Eが(a )では大きいからトンネル電流が流れ、
(b)ではEが小さいからトンネル電流が流れない。第
3図に示すように電流通路となるチャンネルの電位分布
が容量結合すなわち静電誘導効果により制御され、ソー
スからのトンネル電流が制御されることから、本発明の
トランジスタは、静電誘導トンネルトランジスタ(5t
atic   Induced  Tunnel   
T ransist。
n+12.1]13 The impurity density in each region is
The culm has a short culm interval, and the culm has a short source-drain interval. Gate-to-gate spacing is, for example, 2μm
From the above, the source-drain distance is approximately 1000A, and the distance between the source and drain is 1.
It is about 2 to 3 μm from 000A. The thinner the insulating film 16 in contact with n4'12, the more effectively the gate voltage is applied to the n+12 region. is the potential distribution when a positive voltage is also applied to the gate to make it conductive, and (b) is the potential distribution when the gate is at zero potential (the source is also at the same potential) when it is cut off. (a) ), then
Since a positive voltage is applied to the gate, the potential gradient in front of the source becomes steeper, whereas in (b) it becomes more gradual due to the gate voltage. Since the electric field E determined by this gradient is large in (a), a tunnel current flows,
In (b), since E is small, no tunnel current flows. As shown in FIG. 3, the potential distribution of the channel serving as a current path is controlled by capacitive coupling, that is, the electrostatic induction effect, and the tunnel current from the source is controlled. Therefore, the transistor of the present invention is an electrostatic induction tunnel transistor. (5t
atic induced tunnel
Transist.

r:5ITT)と呼ばれる。トンネル電流を多く流そう
とすればn+12領域の不純物密度は高い方が良く、ま
たその厚さは薄い方が良い。
r:5ITT). If a large amount of tunnel current is to flow, the higher the impurity density in the n+12 region, the better, and the thinner the thickness.

例えば厚さは0.2μmから0.03μmといったよう
にである。n+12領域の厚さが薄くなったときには、
ゲート・ゲート間隔も狭くする必要がある。チャンネル
全面をより有効に制御して電流を流すようにするためで
ある。例えば、1μmから0.1μmといったようにで
ある。
For example, the thickness is from 0.2 μm to 0.03 μm. When the thickness of the n+12 region becomes thinner,
It is also necessary to narrow the gate-to-gate spacing. This is to more effectively control the entire surface of the channel to allow current to flow. For example, from 1 μm to 0.1 μm.

絶縁層16は、SiであればSiO2、Si3N4、A
見20.、/IN等もしくはこれらの複合膜、GaAS
であれば、GaO工Ny−8i 、N4、A、1203
、AiN等である。
The insulating layer 16 is made of SiO2, Si3N4, A
See 20. , /IN etc. or a composite film thereof, GaAS
If so, GaO engineering Ny-8i, N4, A, 1203
, AiN, etc.

これまで、ソース領域・ドレイン領域が互いに逆導電型
の高不純物密度領域で構成された構造のトランジスタで
説明してきたが、ソース・ドレインが同導電型の高不純
物密度領域で構成される場合にも、本発明の趣旨を生か
したトランジスタは形成できる。その実施例を第4図に
示す。n48領域31がソース領域、n十領域34がド
レイン領域、35.35)がゲート電極、36が絶縁層
である。p+領域32がソースに対する電位障壁を作る
領域で、いわば真のゲート領域となっている。n領域3
3は殆んど空乏化するようになって、不純物密度が決め
られる。p+領域32の厚さ及び不純物密度は、ソース
n++領域との拡散電位及びn+ドレイン領域との拡散
電位とトレインに加わる電圧で全領域空乏化するように
設定される。n+1ソース領域の不純物密度は、10′
9〜lX10”Cl11−3、p+領域32及びドレイ
ンn’?領域34はそれぞれ5×10〜1Qcm 、n
領域33は10〜1Qcm  程度である。トレインに
正電圧を印加したときのソース・ドレイン方向の電位分
布を第5図に示す。空乏化したp+領域32がソースに
対して障壁を形成している。ソースからの電子注入は、
この障壁により阻止される。その障壁の幅が広いとたと
えゲート電圧で障壁高さを低下させても、トンネル注入
は起らず、障壁の上を越えるキャリアで電流が流れるよ
うになる。すなわち、従来型STTである。しかし、障
壁の幅を1000A以下望ましくは500A以下にする
と、トンネル注入が顕著になる。p 領域32は、動作
状態にある間空乏化するようになされている。厚さWP
と不純物密度N、の値を略々 9X10  cm  <NaW2<5x10’cm−’
のように選定する。例えば、W=500Aとすると、 3.6X1017cm−3<Na  <2x10”cm
−3W=200Aなら 2.25X10′8c+++−’<Na <1.25X
1o +9 c m −3 といったようにである。
So far, we have explained a transistor with a structure in which the source region and drain region are composed of high impurity density regions of opposite conductivity types, but it can also be , a transistor that takes advantage of the spirit of the present invention can be formed. An example thereof is shown in FIG. The n48 region 31 is a source region, the n+ region 34 is a drain region, 35.35) is a gate electrode, and 36 is an insulating layer. The p+ region 32 is a region that forms a potential barrier to the source, and serves as a so-called true gate region. n area 3
3 becomes almost depleted, and the impurity density is determined. The thickness and impurity density of the p+ region 32 are set so that the entire region is depleted by the diffusion potential with the source n++ region, the diffusion potential with the n+ drain region, and the voltage applied to the train. The impurity density of the n+1 source region is 10'
9~1X10"Cl11-3, p+ region 32 and drain n'? region 34 are respectively 5x10~1Qcm, n
The area 33 is about 10 to 1 Qcm. FIG. 5 shows the potential distribution in the source-drain direction when a positive voltage is applied to the train. Depleted p+ region 32 forms a barrier to the source. Electron injection from the source is
blocked by this barrier. If the barrier is wide, even if the gate voltage lowers the barrier height, tunnel injection will not occur, and current will flow due to carriers crossing the barrier. That is, it is a conventional STT. However, when the width of the barrier is set to 1000 A or less, preferably 500 A or less, tunnel injection becomes noticeable. P region 32 is adapted to be depleted during operation. Thickness WP
and impurity density N, approximately 9X10 cm <NaW2<5x10'cm-'
Select as follows. For example, if W=500A, 3.6X1017cm-3<Na<2x10"cm
-3W=200A then 2.25X10'8c+++-'<Na <1.25X
1o +9 cm -3 and so on.

このように構成しておいてグー1〜に正電圧を印加すれ
ば、電位障壁が引き下げられトンネル電流が流れる。も
ちろん、ある程度障壁が低くなれば障壁の上を越えるキ
ャリアの注入も同時に起こるようになる。
With this configuration, if a positive voltage is applied to the gates 1 to 1, the potential barrier is lowered and a tunnel current flows. Of course, if the barrier is lowered to a certain extent, carrier injection over the barrier will also occur at the same time.

これまでは、トンネル注入を制御するゲート電極は基本
的に1つのものを説明してきた。もちろん、分割された
ゲートも含まれてはいるがトンネル注入制御ゲート電極
を複数個設けて、制御電圧を加えるゲートを選ぶことに
よって機能を持った動作を行な4)辻ることがて゛きる
。1その例をしデル的に第C)図([示1゜11+″4
1:ソース領域、n 44ニドレイン領域、45.45
’、46.46′はグー1〜電極、41′、44′はソ
ース電極、ドしツイン電極である5、この例では、4G
、46 ’ 4qt浮遊電極になされており、グー1−
電圧は45.45′に印加される、3ドレイン(こ大き
な正電圧を印1111 ’uた状態で、グー1−45に
正電圧を印加すると下側表面に近い所を電子は流れる。
So far, we have basically explained one gate electrode that controls tunnel injection. Of course, divided gates are included, but by providing a plurality of tunnel injection control gate electrodes and selecting the gate to which a control voltage is applied, a functional operation can be performed. 1. For example, in Figure C) ([shown 1゜11+''4
1: Source region, n 44 Ni drain region, 45.45
', 46.46' are the goo 1 ~ electrodes, 41', 44' are the source electrodes, and doshi twin electrodes 5. In this example, 4G
, 46' 4qt floating electrode, Goo 1-
The voltage is applied to the drain 45, 45', and when a positive voltage is applied to the drain 1-45 with a large positive voltage 1111'u applied, electrons flow near the lower surface.

この流れている電子のうち、高エネルギーに加速された
電子は絶縁層47のバリアを越えて、浮遊ゲート4Gに
流れ込み蓄積される。浮遊ゲート46に電子が蓄積され
ると、負に帯電するから下側表面近傍から電子は遠ざけ
られる。上側ゲート電極45’、4G)でもIF5様の
ことが行なえる。このようにドレインやグー1〜に正で
大きな電圧を加えて浮遊グー1へに電子を蓄積させると
、その表面近傍は電子が流れなくなる。正規の動作電圧
にトレイン電圧、ゲート電圧を戻して動作させると、次
のような動作になる。4G、4G)がい−4゛れも)電
1“ハ\書き込まれていイ[1いとさもよ、45.45
′に+Fのグー1〜電極を印加寸◇とぞれぞれの表面に
冶って電子は治れる。もし、4G、46′に雷イが出き
込まれていると、45.45 1;電圧4加えた状態て
電子は中心付近に集中して流れろ。浮遊グー1−に電子
がジ1.!込まれてい41いグー1−に電斤庖+lt1
えれば、イの表面に沿う形で電子は流れる1、(二の例
では、ドレインを1って示したが、例えは、土、中、下
というように3つに分けて設けて、イねぞれ分離してお
りば、あるいはドレインをショットキ接合に1)でおけ
ば、電子の占き込み状態によって、電流の流れるドし・
インがかわることになる。
Among these flowing electrons, electrons accelerated to high energy cross the barrier of the insulating layer 47, flow into the floating gate 4G, and are accumulated. When electrons are accumulated in the floating gate 46, the floating gate 46 becomes negatively charged and is therefore moved away from the vicinity of the lower surface. The same thing as IF5 can also be done with the upper gate electrode 45', 4G). When electrons are accumulated in the floating goo 1 by applying a large positive voltage to the drain or the goo 1 as described above, electrons no longer flow near the surface thereof. When the train voltage and gate voltage are returned to the normal operating voltage and the device is operated, the following operation occurs. 4G, 4G) Gai-4゛Remo) Electric 1 "Ha\ written in [1 and the same, 45.45
Electrons can be cured by applying +F goo 1 to ◇ to each surface. If lightning is being sent in and out of 4G and 46', electrons will concentrate near the center and flow with 45.45 1; voltage 4 applied. The electrons in the floating goo 1-1. ! Contains 41 goo 1- and electric loaf +lt1
In other words, electrons flow along the surface of A (1). If the drains are separated, or if the drain is placed in a Schottky junction as shown in step 1), the current flow will depend on the state of the electrons.
The inn will change.

例えば、4G、46′に電子が占き込まれていると号れ
ば、45.45’のいずれかもしくは両方に電圧を加え
た場合、殆んどの電流は中のドレインに流れる。4Gが
書き込まれており、46 は占き込まれていないとすれ
ば、45に電圧を加えたとき中、45′に電圧を加えた
とき上、両者に加えた時は中、上のドレインに電流が流
れるにうにづることができる。
For example, if electrons are occupied in 4G and 46', if a voltage is applied to either or both of 45 and 45', most of the current will flow to the drain inside. Assuming that 4G is written and 46 is not written, when voltage is applied to 45, the middle and upper drains are applied when voltage is applied to 45', and to the middle and upper drains when voltage is applied to both. It can be imagined that electric current flows.

ソースからトンネル注入された電子が、トレインまでの
走行領域をドリフトで走行する場合と、殆んど散乱を受
けず(こ次第に加速されながら走行する場合とがある。
There are cases in which electrons tunnel-injected from the source travel in the travel region up to the train by drifting, and cases in which they travel with almost no scattering (while being gradually accelerated).

この両者が現れるのは、電子が散乱を受ける平均自由行
程と走行空間の距離の関係で決まる。走行空間距離が自
由行程に比べて十分長ければ、ドリフト走行になる。そ
うでなければ初速麿と電界により次第に加速される走行
となる。Siに比べてQa Asの自由行程は数倍以上
長いと言われている。従って、GaAsの方が後右の電
子の運動が坦れ易い。
The appearance of both is determined by the relationship between the mean free path of the electron and the distance in the traveling space. If the traveling space distance is sufficiently long compared to the free path, the vehicle will drift. Otherwise, the vehicle will be running gradually accelerated by the initial velocity and the electric field. It is said that the free path of Qa As is several times longer than that of Si. Therefore, the motion of electrons on the rear right is more likely to be flattened in GaAs.

電子が散乱をあまり受けずに走行するようになると電子
の走行速度は早くなり、走行時間から決まる上限周波数
は極めて高くなる。
When electrons travel with less scattering, their traveling speed increases, and the upper limit frequency determined from the traveling time becomes extremely high.

これまでの実施例では、トンネル注入を起すソースとソ
ースに直接隣接する領域の不純物密度は空間的に一様で
あるJ−うに述べてきたが、必ずしも一様である必要は
ない。トンネル注入をもっとも強く起したい所の不純物
密度を高くしてトンネル注入効率を高くすることしでさ
る本発明の半導体デバイスがここで述べた実施例に限定
されないことはもちろんである。導電)りを反転し1、
:構造でもよいことはもらろんである。いずれにしても
、ソースからのキャリフッをトンネル注入で注入させ、
その注入量をグー1−電圧及びトレイン電圧の静電誘導
効果で制御する構造の半導体デバイスであればよい。j
・ンネル注入を効率良く起すには、不純物密度は高い方
がよい。しかもその領域を空乏化して容量結合で電位分
布制御しようというのであるから、本発明の半導体デバ
イスは、本質的に微細化されたデバイスである。個別デ
バイスはもとより超高密度超高速集積回路に最適である
。デバイスの寸法が小さくなればなる程有効である。し
かも、高不純物密度領域から直接l〜ンネルでキトリア
を注入させているから、ソース近傍のキヤリアの蓄積効
果が極めて少なく高速動作に極めて適する。
In the embodiments described above, it has been described that the impurity density in the source where tunnel injection occurs and the region directly adjacent to the source is spatially uniform; however, it is not necessarily necessary that the impurity density be uniform. It goes without saying that the semiconductor device of the present invention, which increases the tunnel injection efficiency by increasing the impurity density where tunnel injection is desired to occur most strongly, is not limited to the embodiments described here. Reverse the conductivity) 1,
: Of course it's good to have a good structure. In any case, the carrier fluid from the source is injected by tunnel injection,
Any semiconductor device may be used as long as it has a structure in which the amount of implantation is controlled by the electrostatic induction effect of the G1-voltage and the train voltage. j
・In order to cause channel implantation to occur efficiently, it is better to have a high impurity density. Moreover, the semiconductor device of the present invention is essentially a miniaturized device because this region is depleted and the potential distribution is controlled by capacitive coupling. It is ideal for not only individual devices but also ultra-high density and ultra-high speed integrated circuits. The smaller the dimensions of the device, the more effective it is. Moreover, since the chitria is directly implanted from the high impurity density region by channel, the effect of carrier accumulation near the source is extremely small, making it extremely suitable for high-speed operation.

ここでは、ソース領域を高不純物密度領域で形成した例
を示したが、ソースを金属やシリサイドにして、ショッ
トキ接合にして、ショットキ接合前面の電位勾配を急峻
にしてトンネル注入を起させることも、もちろんである
Here, we have shown an example in which the source region is formed in a high impurity density region, but it is also possible to make the source a Schottky junction by using metal or silicide, and to cause tunnel injection by making the potential gradient in front of the Schottky junction steep. Of course.

本発明の半導体デバイスは、従来公知の製造技術で作る
ことができる。
The semiconductor device of the present invention can be manufactured using conventionally known manufacturing techniques.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は半導体材料をQa ASとして計算した結果、
第2図及び第3図はソース・ドレイン方向の電位分布で
(a )は導通状態、(b)は遮断状態を示す図、第4
図乃至第6図は本発明の実施例を示す断面図である。
Figure 1 shows the results of calculations using semiconductor materials as Qa AS.
Figures 2 and 3 are potential distributions in the source-drain direction, with (a) showing the conduction state and (b) the cut-off state;
6 through 6 are cross-sectional views showing embodiments of the present invention.

Claims (6)

【特許請求の範囲】[Claims] (1)高不純物密度の第1導電型のソースとドレイン領
域、ソースとドレインの間のチャンネル領域がソースに
接する少なくとも一部が、高不純物密度の第1導電型と
は反対導電型の薄い領域とドレインに接する第1導電型
の不純物密度の低い領域から構成され、ソースとチャン
ネルの少なくとも一部よりトンネル注入をさせ、チャン
ネルに接して設けられたゲート領域により制御を行なう
ことを特徴とするトンネル注入制御半導体デバイス。
(1) A thin region where at least a portion of the source and drain regions of the first conductivity type with high impurity density and the channel region between the source and drain is in contact with the source is a conductivity type opposite to the first conductivity type with high impurity density. and a region with a low impurity density of the first conductivity type in contact with the drain, the tunnel is implanted through at least a portion of the source and the channel, and is controlled by a gate region provided in contact with the channel. Injection control semiconductor device.
(2)前記高不純物密度ソース領域にほぼ接する一部に
だけ反対導電型高不純物密度領域を設け、トンネル効果
の起る方向を決めることを特徴とする前記特許請求の範
囲第1項記載のトンネル注入制御半導体デバイス。
(2) A tunnel according to claim 1, characterized in that a high impurity density region of an opposite conductivity type is provided only in a portion substantially in contact with the high impurity density source region to determine the direction in which the tunnel effect occurs. Injection control semiconductor device.
(3)前記制御電極を絶縁型ゲートとしたことを特徴と
する前記特許請求の範囲第1項又は第2項記載のトンネ
ル注入制御半導体デバイス。
(3) The tunnel injection control semiconductor device according to claim 1 or 2, wherein the control electrode is an insulated gate.
(4)前記制御電極を接合型ゲートとしたことを特徴と
する前記特許請求の範囲第1項又は第2項記載のトンネ
ル注入制御半導体デバイス。
(4) The tunnel injection control semiconductor device according to claim 1 or 2, wherein the control electrode is a junction type gate.
(5)前記制御電極をショットキゲートとしたことを特
徴とする前記特許請求の範囲第1項又は第2項記載のト
ンネル注入制御半導体デバイス。
(5) The tunnel injection control semiconductor device according to claim 1 or 2, wherein the control electrode is a Schottky gate.
(6)前記制御電極を複数個設けたことを特徴とする前
記特許請求の範囲第1項乃至第5項のいずれか一項に記
載のトンネル注入制御半導体デバイス。
(6) The tunnel injection control semiconductor device according to any one of claims 1 to 5, characterized in that a plurality of the control electrodes are provided.
JP62250183A 1987-10-01 1987-10-01 Tunnel injection control semiconductor device Granted JPS6399580A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62250183A JPS6399580A (en) 1987-10-01 1987-10-01 Tunnel injection control semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62250183A JPS6399580A (en) 1987-10-01 1987-10-01 Tunnel injection control semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP55151849A Division JPS5775464A (en) 1980-10-28 1980-10-28 Semiconductor device controlled by tunnel injection

Publications (2)

Publication Number Publication Date
JPS6399580A true JPS6399580A (en) 1988-04-30
JPH046111B2 JPH046111B2 (en) 1992-02-04

Family

ID=17204049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62250183A Granted JPS6399580A (en) 1987-10-01 1987-10-01 Tunnel injection control semiconductor device

Country Status (1)

Country Link
JP (1) JPS6399580A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0256972A (en) * 1989-05-18 1990-02-26 Semiconductor Res Found Tunnel injection type transit-time effect three-terminal semiconductor device
JP2007115861A (en) * 2005-10-20 2007-05-10 Toyota Motor Corp Heterojunction transistor
JP2014013893A (en) * 2012-06-15 2014-01-23 Imec Tunnel field effect transistor device and method for making said device
JP2014041974A (en) * 2012-08-23 2014-03-06 Toshiba Corp Semiconductor device and method of manufacturing the same
JP2015159252A (en) * 2014-02-25 2015-09-03 富士通株式会社 Semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5343483A (en) * 1976-10-01 1978-04-19 Handotai Kenkyu Shinkokai Semiconductor device
JPS5357769A (en) * 1976-11-04 1978-05-25 Mitsubishi Electric Corp Electrostatic induction transistor
JPS55151849A (en) * 1979-05-17 1980-11-26 Fujitsu Ltd Digital conference telephone system
JPS5775464A (en) * 1980-10-28 1982-05-12 Semiconductor Res Found Semiconductor device controlled by tunnel injection
JPS6435508A (en) * 1987-07-31 1989-02-06 Fujikura Ltd Optical fiber incidence and exit device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5343483A (en) * 1976-10-01 1978-04-19 Handotai Kenkyu Shinkokai Semiconductor device
JPS5357769A (en) * 1976-11-04 1978-05-25 Mitsubishi Electric Corp Electrostatic induction transistor
JPS55151849A (en) * 1979-05-17 1980-11-26 Fujitsu Ltd Digital conference telephone system
JPS5775464A (en) * 1980-10-28 1982-05-12 Semiconductor Res Found Semiconductor device controlled by tunnel injection
JPS6435508A (en) * 1987-07-31 1989-02-06 Fujikura Ltd Optical fiber incidence and exit device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0256972A (en) * 1989-05-18 1990-02-26 Semiconductor Res Found Tunnel injection type transit-time effect three-terminal semiconductor device
JP2007115861A (en) * 2005-10-20 2007-05-10 Toyota Motor Corp Heterojunction transistor
JP2014013893A (en) * 2012-06-15 2014-01-23 Imec Tunnel field effect transistor device and method for making said device
JP2014041974A (en) * 2012-08-23 2014-03-06 Toshiba Corp Semiconductor device and method of manufacturing the same
JP2015159252A (en) * 2014-02-25 2015-09-03 富士通株式会社 Semiconductor device

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Publication number Publication date
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