JPS6417425A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6417425A
JPS6417425A JP17287287A JP17287287A JPS6417425A JP S6417425 A JPS6417425 A JP S6417425A JP 17287287 A JP17287287 A JP 17287287A JP 17287287 A JP17287287 A JP 17287287A JP S6417425 A JPS6417425 A JP S6417425A
Authority
JP
Japan
Prior art keywords
film
impurity
dopant added
dopant
annealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17287287A
Other languages
Japanese (ja)
Inventor
Yoshiharu Hidaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP17287287A priority Critical patent/JPS6417425A/en
Publication of JPS6417425A publication Critical patent/JPS6417425A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To form an impurity diffusion layer, which is high in impurity concentration and small in impurity depth, with good controllability, by forming a bilayer structure consisting of a film with a dopant added in its diffusion region and of a film with no dopant added there, and by performing an annealing process. CONSTITUTION:Bilayer structure, consisting of a film 5 with a dopant added in its diffusion region 4 of a semiconductor substrate 1 and of a film 6 with no dopant added there, is formed and next an annealing process is performed. Hence the dopant high in its vapor pressure can be prevented from diffusing into an atmosphere at the time of annealing. Consequently an impurity diffusion layer 4 high in impurity concentration and small in impurity depth can be secured in a short annealing time even if the film with the dopant added therein is made thin.
JP17287287A 1987-07-13 1987-07-13 Manufacture of semiconductor device Pending JPS6417425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17287287A JPS6417425A (en) 1987-07-13 1987-07-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17287287A JPS6417425A (en) 1987-07-13 1987-07-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6417425A true JPS6417425A (en) 1989-01-20

Family

ID=15949868

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17287287A Pending JPS6417425A (en) 1987-07-13 1987-07-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6417425A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02208929A (en) * 1989-02-08 1990-08-20 Rohm Co Ltd Manufacture of semiconductor device
JP2006310373A (en) * 2005-04-26 2006-11-09 Shin Etsu Handotai Co Ltd SOLAR CELL MANUFACTURING METHOD, SOLAR CELL, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02208929A (en) * 1989-02-08 1990-08-20 Rohm Co Ltd Manufacture of semiconductor device
JP2006310373A (en) * 2005-04-26 2006-11-09 Shin Etsu Handotai Co Ltd SOLAR CELL MANUFACTURING METHOD, SOLAR CELL, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

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