JPS642018B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power line transport system in which a parent device and a plurality of slave devices are connected via a power line, and a load connected to the slave devices is controlled by a control signal transmitted from the parent device. , a slave logic unit that outputs an output pulse after checking all signal formats such as addresses, and a re-triggerable one-shot multi unit that is triggered by the output pulse and outputs a pulse with a width approximately equal to the time required for one transmission. an output of the one-shot multi-circuit;
Output when a carrier signal is present on the power line
The present invention relates to a load control circuit in a power line transport system, characterized in that the load is controlled by an AND output with a busy output.

An object of the present invention is to improve the responsiveness when controlling a load connected from a master device to a slave device on and off, particularly when the load is turned off, so that the load can be operated in real time.

Generally, a power line transport system controls loads 3, 3 connected to slave devices 2, 2 by control signals from a parent device 1, as shown in FIG. The control signal is transmitted by superimposing a high frequency signal on the power line 4,
0 as shown in Figure 2b for the power supply waveform in Figure 2a
Transmit in synchronization with the cross waveform. In order to control a plurality of loads 3, 3 in this manner, multiplexing of the signals is performed. All control signals are sent as digital data, and this data format is
As shown in the figure, there is a start mark indicating the start of data, a mode indicating control details, and which slave device 2, 2.
It consists of an address code that indicates which signal is being sent.
Each slave device 2 has its own address, and operates according to the mode when the address code of the control signal sent from the master device 1 matches its own address. As a result, the parent device 1 has multiple child devices 2, 2,
In the example of FIG. 3, the address code is 8 bits, so 256 slave units 2, 2 can be operated individually.

In the power line transport system as described above, the slave units 2, 2 are constructed as shown in FIG. Fourth
In the figure, 5 is a modem, which is an interface between a digital circuit and an analog circuit, and modulates and demodulates a carrier signal. Reference numeral 6 denotes a reply data creation section, which creates reply data that informs the on or off state of the load 3 in response to the control signal from the parent device 1. 7 is the frequency test section,
Frequency count of carrier signal. 8 is a timing signal generating section which generates timing signals and carrier signals for all the circuits shown in the block circuits. Reference numeral 9 denotes a received data reproducing section, which reproduces the received data based on the results verified by the frequency verification section 7. Reference numeral 10 denotes a reference signal generating section, which generates a reference signal necessary for the timing signal generating section 8. Reference numeral 11 denotes an address setting section for setting the address of the child device 2. Reference numeral 12 denotes an address determination unit that compares the address of the transmitted control signal with the address set in the slave device 2 itself to determine whether they match. Reference numeral 13 denotes a mode determination unit that determines the mode of the transmitted control signal. Reference numeral 14 denotes an output section, which outputs an output for turning the load 3 on or off according to the mode data if the addresses match according to the mode judgment section 13 and the address judgment section 12. In other words, child device 2
The modem 5 demodulates the carrier signal which is carried in synchronization with the 0 cross in accordance with the control signal from the master device 1, and the frequency test section 7 counts the frequency of the carrier signal.
It is detected where the carrier signal is located between the falling edge and the falling edge of the 0 cross, and then the received data reproducing section 9 reproduces the received data using the signal from the frequency verification section 7. If the address set in slave unit 2 itself matches the address of the transmitted control signal, it controls load 3 according to the received mode and creates reply data to master unit 1. and sends a reply through modem 5.

Next, the master unit 1 is constructed as shown in FIG. 5, and 15 is a modem, which is the same as the modem 5 of the slave unit 2. Reference numeral 16 denotes a transmission data creation section that creates control signals based on signals from the switch input section 17, latch 18, and the like. The switch input section 17 is the switch 19
Converts the signal into a digital signal. Reference numeral 20 indicates a frequency verification section, and reference numeral 21 indicates a timing signal generation section, each of which is the same as that of the slave device 2. Reference numeral 22 denotes a received data reproducing section, which reproduces the received data based on the result verified by the frequency verification section 20, and sends a retransmission command to the transmitted data creation section 16 if the received data is different from its own transmitted data. The switch 19 is a control command switch for the load 3 connected to the slave unit 2 set externally. Reference numeral 23 denotes a reference signal generating section, which is the same as that of slave unit 2. 24 is an address determination unit which latches the transmitted address. Reference numeral 25 denotes a reply data determination unit which determines the reply data transmitted from the slave device 2. The latch 18 stores the address of the slave unit 2 and the state of the load 3 connected to the slave unit 2. That is, when the switch 19 is pressed, the master device 1 creates corresponding transmission data and transmits a control signal to the slave device 2 through the modem 15. At that time, if the data is being received at the same time and the data that it sent and the data that it received do not match, it will retransmit it. Then, when reply data is returned from the slave unit 2 to which the control signal was correctly transmitted, the address and reply data at that time are latched. Therefore, the master device 1 can control and monitor the slave device 2 at the same time.

As mentioned above, the parent device 1 creates logic level signals according to the format shown in FIG.
This signal is modulated into a high frequency signal by the modem 15 and superimposed on the power line 4. The slave unit 2 checks the carrier frequency of the received signal to determine whether there is a signal on the transmission line 4.
The demodulated waveform is decoded, and if the addresses match, control is performed according to the mode.

Figures 6a to 6d are timing charts showing normal control conditions in such a system;
FIG. 8 and FIG. 8 are examples of peripheral circuits of the slave device 2 and the master device 1, respectively. In FIG. 7, reference numeral 26 denotes a slave logic section, excluding the modem 5 shown in FIG. control. Further, in FIG. 8, 28 is a parent device logic section, which connects the modem 15 and switch 1 in FIG.
This is the part excluding 9. As shown in FIG. 6, the output pulse is output when one signal is received and the addresses match. In the case of FIG. 6, the switch 19 is turned on and then turned off. In the case of these controls, the actual operation always lags behind the input operation of the switch 19 by one signal transmission time _T1 . However, when controlling the load 4 that takes a long time from the on operation to the off operation, this time T ₁ does not pose a problem. for example,
If T ₁ is 0.5 seconds, 0.5 from the operation of switch 19
The operation will be delayed by a few seconds. However, if the load 4 is to be turned on for a short period of time and the operator decides the timing to stop the load 4 depending on the amount of operation, the delay in T1, especially the delay when stopping the load ₄ becomes a problem. As an example, when the movable base 29 is moved vertically and horizontally by the vertical drive motor 30 and the left and right drive motors 31 as shown in FIG. When performing control, the operator operates to stop the movable base 29 at an appropriate position while checking how much it has moved.
At this time, the stopping position shifts due to the delay of _T1 mentioned above.

The present invention has been made in view of this point, and will be explained in detail below with reference to Examples.

FIG. 10 is a block circuit diagram of the parent unit 1. The difference from the conventional example shown in FIG. , and the point where the transmission continues while the switch 19 is pressed. Therefore, by releasing the switch 19, the control signal can be immediately stopped even in the middle of one signal format. 11th
The figure is a block circuit diagram of the slave unit 2, in which only on-pulses are used as the output of the slave logic unit 26. This output is output after checking all the signal formats such as the address, and this output is input to the retriggerable one shot multi circuit 33.
A pulse with a width approximately equal to the time required for one transmission is output. Also, a busy output indicating that there is a carrier signal on the power line 4 is used. This busy output is
It is output from the frequency verification section 7 in the figure, and is output if the signal frequency on the power line 4 is correct, and is output regardless of the signal format such as mode and address. This busy output and the output of the one shot multi circuit 33 are connected to the second AND gate 3.
4, and its output operates the relay 35.

Next, the operation will be explained using timing charts shown in FIGS. 12a to 12f. Figure 12a shows switch 1
Using the 9 input waveform, press load 4 only as long as you want it to turn on. Further, by turning on the switch 19, a trigger input is given to the parent logic unit 28.
Note that this switch 19 is a push-type non-lock switch. FIG. 12b shows the transmitted signal, which continues to be sent while the switch 19 input is present. Also, when the switch 19 is released, the first
The AND gate 32 immediately stops the signal. Figure 12c shows the output pulse waveform.The output pulse is output only when one signal format is received and the mode and address are correct.The operation is 1.
Repeated every time received. Figure 12d is the first
The output waveform of the one-shot multi-circuit 33 triggered by the output pulse shown in FIG. 2c is such that each time it is triggered, the output maintains the "H" level for the time required for one transmission from that point. Therefore, if the signal is turned on and transmitted many times, the output will remain at the "H" level during that time. FIG. 12e shows the busy output, which is at the "H" level while there is a signal on the power line 4.
Figure 12f shows the output of the second AND gate 34.This output will not be output unless the mode and address are correct, and moreover, it will go to the "L" level immediately when the switch 19 in the parent device 1 is released. . Therefore, the switch 19 is turned on and off, and the load 4 is turned on.
Looking at the off-state relationship, there is a delay of _T1 from when the switch 19 is turned on until the load 4 is turned on, as in the conventional example, but when the switch 19 is turned off, the load 4 is also turned off immediately. Therefore, the switch 19 can be held down while transmitting data n times until the required time for the load 4 is reached, and the switch 19 can be freely stopped when necessary. can also be easily controlled.

As described above, the present invention includes a parent logic unit that creates and outputs transmission signals such as address signals and control signals, and a main logic unit that is pressed while continuing to control the load.
The parent device is composed of a push-type non-lock switch that provides a trigger input to the parent device logic section, and a first AND gate that takes the logical product of the output of the parent device logic section and the output of the switch. A slave logic unit that outputs an output pulse after checking all signal formats such as addresses, and a retriggerable one-shot multi-circuit that is triggered by the output pulse and outputs a pulse with a width approximately equal to the time required for one transmission. and a second AND gate that controls the load by calculating the AND of the output of the one-shot multi-circuit and the busy output that is output when a carrier signal is present on the power line. Then, by turning on the switch, a trigger input is given to the parent logic unit to send a transmission signal from the parent logic unit, and the output of the parent logic unit and the output of the switch are ANDed by the first AND gate. The output is transmitted to the slave device, and on the slave side, the one-shot multi-circuit is driven by the output of the slave logic section, and the one-shot multi-circuit output and the busy output are logically ANDed by a second AND gate. The load is controlled by the output, and by turning off the switch on the parent device, the output of the first AND gate disappears, so the busy output on the child device disappears, and the output of the second AND gate disappears. As a result, the load can be turned off at the same time as the switch is turned off, which improves the response when controlling the load connected from the parent unit to the slave unit, especially when it is turned off. This has the advantage of being able to be improved and operated in real time.

[Brief explanation of drawings]

Figure 1 is a basic circuit diagram of a general power line transport system, Figures 2a and b are voltage waveform diagrams of the same main parts as above, and Figure 3 is a basic circuit diagram of a general power line transport system.
The figure shows the control signal format as above, Figure 4 is a block circuit diagram of the slave unit as above, Figure 5 is a block circuit diagram of the master unit as above, and Figures 6a to 6d show the control status of the conventional power line transport system. FIG. 7 is an operating circuit diagram of the slave device, FIG. 8 is an operating circuit diagram of the parent device, FIG. 9 is a perspective view of an application example of the above, and FIG. 10 is an example of the present invention. FIG. 11 is an operation circuit diagram of the master device of the embodiment, FIG. 11 is an operation circuit diagram of the child device of the same example, and FIGS. 12 a to 12 f are operation timing charts of the same example. 1...Main device, 2...Slave device, 3...Power line, 4...
. . . Load, 19 .

Claims (1)

[Claims] 1 Connect the master unit and multiple slave units via power lines,
In a power line transport system in which a load connected to a slave device is controlled by a control signal transmitted from a parent device, a parent device logic section that creates and outputs transmission signals such as address signals and control signals, and a logic section that controls the load. The parent device is composed of a push-type non-lock switch that, when pressed for as long as the switch is pressed, provides a trigger input to the parent device logic section, and a first AND gate that takes the logical product of the output of the parent device logic section and the output of the switch. There is also a slave logic unit that outputs an output pulse after checking all address and other signal formats from the parent unit, and a re-trigger unit that is triggered by the output pulse and outputs a pulse with a width approximately equal to the time required for one transmission. a possible one-shot multi-circuit, an output of the one-shot multi-circuit,
A load operation circuit in a power line transport system, characterized in that a slave device is constituted by a second AND gate that controls the load by performing a logical product with a busy output that is output when a carrier signal is present on the power line. .