JPS6429826U - - Google Patents

Info

Publication number
JPS6429826U
JPS6429826U JP1987123157U JP12315787U JPS6429826U JP S6429826 U JPS6429826 U JP S6429826U JP 1987123157 U JP1987123157 U JP 1987123157U JP 12315787 U JP12315787 U JP 12315787U JP S6429826 U JPS6429826 U JP S6429826U
Authority
JP
Japan
Prior art keywords
wiring pattern
semiconductor chip
semiconductor device
void
impaired
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987123157U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987123157U priority Critical patent/JPS6429826U/ja
Publication of JPS6429826U publication Critical patent/JPS6429826U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structure Of Printed Boards (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案の構成を示す図、第２図は本考
案に係る配線パターン構造を適用した半導体装置
の一例を示す図、第３図は第２図における第２層
配線パターンの平面図、第４図は半導体装置とし
ての密着型イメージセンサの製造工程を示す図で
ある。 〔符号の説明〕、１……半導体チツプ、２……
配線パターン、３……空孔、１０，２０……セラ
ミツクス基板、１１ａ，２１ａ〜２１ｄ……第１
層配線パターン、１２，２２……絶縁層、１３，
２３……第２層配線パータン、１４，２４……グ
レースパターン、１５，２５……コンタクトホー
ル、１６ａ，２６……クロム電極パターン、１７
，２７……光電変換膜、１８ａ，２８……透明電
極。

Claims (1)

  1. 【実用新案登録請求の範囲】 導電性金属により形成され、半導体チツプ１が
    ボンデイングされるべき配線パターン２の構造で
    あつて、 当該配線パターン２に半導体チツプに対する電
    気的特性を損わない範囲で空孔３を形成したこと
    を特徴とする半導体装置における配線パターン構
    造。
JP1987123157U 1987-08-13 1987-08-13 Pending JPS6429826U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987123157U JPS6429826U (ja) 1987-08-13 1987-08-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987123157U JPS6429826U (ja) 1987-08-13 1987-08-13

Publications (1)

Publication Number Publication Date
JPS6429826U true JPS6429826U (ja) 1989-02-22

Family

ID=31371751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987123157U Pending JPS6429826U (ja) 1987-08-13 1987-08-13

Country Status (1)

Country Link
JP (1) JPS6429826U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106069U (ja) * 1986-12-27 1988-07-08

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58153339A (ja) * 1982-03-05 1983-09-12 Mitsubishi Electric Corp 混成集積回路体の製造方法
JPS61295656A (ja) * 1985-06-25 1986-12-26 Toshiba Corp イメ−ジセンサ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58153339A (ja) * 1982-03-05 1983-09-12 Mitsubishi Electric Corp 混成集積回路体の製造方法
JPS61295656A (ja) * 1985-06-25 1986-12-26 Toshiba Corp イメ−ジセンサ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106069U (ja) * 1986-12-27 1988-07-08

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