JPS643341B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a master slice type semiconductor integrated circuit device with a high cell utilization rate, and particularly to its structure.

In recent years, the use of ICs in communication devices, computers, etc. has progressed, and master slice type LSIs have been increasingly used. Among the master slice methods, the so-called so-called complementary insulated gate field effect transistor is used from the viewpoint of speed and power saving.
CMOS types are often used. In the master slicing method, for example, a MOS transistor is formed at a predetermined position, and contact holes that can be independently connected to the source, drain, and gate of the transistor are formed, and an aluminum conductive film is formed in one layer.
It is formed into a layer or two-layer structure and connected to each other to form a circuit. In this case, ideally any circuit should be realized with a minimum set of basic transistors (called cells).

Figure 1a shows an example of a conventional CMOS type master slice.

In FIG. 1a, P
After forming a well layer 2, forming a thin gate oxide film 10 in the transistor formation area, and forming an n ⁺ polysilicon layer, gate polysilicon 3A, 3B and feedthrough polysilicon layer 3C are patterned, and a P channel is formed. MOS transistor (hereinafter referred to as
PMOST) source, drain layer 6 and N
Channel MOS transistor (hereinafter referred to as NMOST)
ion implantation of P-type impurities into the substrate voltage application part 5 of the NMOST source/drain layer 4.
After ion implantation of N-type impurities into the substrate voltage application section 7 of the PMOST, an insulating film is formed on the entire surface, and the source and drain layers 4 and 6, the substrate voltage application section 5 and 7, and the polysilicon layer 3 are formed. A contact hole 8 is drilled in the required part of the base plate, and a base is formed. In the figure, VD line 9A and VSS line 9B, which are part of the aluminum film.
It also shows.

Incidentally, such a structure can be expressed in a simple form as shown in FIG. 1b, and such an expression will be used below for convenience of explanation.

Next, we will form the dynamic flip-flop shown in Figure 2a using a conventional CMOS type master slice. In this figure, TG represents a transfer gate, and φ represents a clock having an inverse relationship. In this example, as shown in FIG. 2b, the transistor groups indicated by X and Y are unused, and the total number of transistors should be 8, but 12 are used. This means that the cell utilization rate will decrease. Further, the wiring is quite complicated, and the unused transistors shown in X and Y cause an increase in stray capacitance. As described above, the conventional structure has the drawbacks of decreasing cell utilization rate and increasing stray capacitance.

An object of the present invention is to provide a master slice semiconductor integrated circuit device that solves this conventional drawback.

A feature of the present invention is, for example, a group of a (≧2) second conductivity type transistors connected in series with a second conductivity type source/drain layer on a first conductivity type silicon substrate;
A first conductivity type transistor groups connected in series in a first conductivity type source/drain layer formed in a second conductivity type well layer are regularly arranged, and at least one conductivity type transistor group is Each of the a transistors is in a master slice semiconductor integrated circuit device in which each transistor of the a transistor group of the other conductivity type is connected by a gate polysilicon layer.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows the structure of a CMOS type master slice integrated circuit device according to an embodiment of the present invention. Third
In the central part of figure a, two PMOS transistors 1 are connected in series with a P ⁺ source-drain layer 6.
Two NMOS transistors 10 connected in series with 0C and 10D and N ⁺ source/drain layer 4B
A, 10B, and gate polysilicon 3B is
Apply gate voltage to PMOST10D and NMOST10A, and gate polysilicon 3A is applied to PMOST10A.
NMOST1 of C and other N ⁺ source drain layer 4A
Give a gate voltage of 0B. FIG. 3b shows the left end portion. The P ⁺ source/drain layer 6B is the same as the central part, but the leftmost P ⁺ source/drain layer 6A is the gate polysilicon layer 3.
A' is the gate voltage of PMOST10C. Although the right end is omitted, the gate polysilicon layer 3
B' gives only the gate voltage of NMOST10B.

According to the structure of the present invention, the circuit shown in FIG. 2a described above can be realized in the form shown in FIG. Only two additional pieces are required, and wiring is simple. That is, it is possible to realize a significant improvement in cell utilization rate, and it is expected that characteristics will be improved by reducing stray capacitance.

In addition, in FIG. 3b, polysilicon 3A' is
The gate voltage was only applied to PMOST, but as shown in FIG.
As shown in the central part of A', all gate polysilicon layers are made into PMOST by using NMOST of N ⁺ source/drain layer 42' instead of N ⁺ source/drain layer ⁴ '.
The gate voltage can be applied to each pair of NMOSTs. Alternatively, as shown in FIG. 5, a gate polysilicon layer 3A'' may be formed in the center.Also, two series PMOST and NMOST
Instead, PMOST is composed of three or more pieces in series.
NMOST may also be used.

[Brief explanation of drawings]

Figures 1a and 1b are structural examples of basic cells of conventional CMOS type master slice integrated circuit devices; Figure 1a is a plan view, Figure 1b is a simple structural diagram of Figure 1a, and Figure 2 2a is a circuit diagram of a dynamic flip-flop circuit, FIG. 2b is an implementation example of the master slice method of FIG. 1, and FIGS. 3a and b are CMOS typewriter slice integrated circuits according to an embodiment of the present invention. FIG. 3A shows the central part, FIG. 3B shows the left end part, and FIG. 4 shows the dynamic frits of the circuit shown in FIG. 2A in the structure of the embodiment of the present invention. FIG. 5 is a simple structural diagram for explaining another embodiment of the present invention. In the figure, 1... n-type silicon substrate, 2
... P well layer, 3 ... polysilicon layer, 4 ...
N ⁺ source/drain layer, 5...NMOST substrate voltage applied P ⁺ layer, 6...P ⁺ source/drain layer, 7...
PMOST substrate voltage applied n ⁺ layer, 8...contact hole, 9...aluminum conductive film.

Claims (1)

[Claims] 1 A plurality of sets of a plurality of second conductivity type transistors each having a source and a drain region adjacent to the first conductivity type substrate connected in series are formed in a second conductivity type well layer in the first conductivity type substrate. In a master slice semiconductor integrated circuit device in which a plurality of sets of a plurality of first conductivity type transistors are formed in which source and drain regions adjacent to each other are connected in series,
One second conductivity type transistor in each of the plurality of sets of second conductivity type transistors corresponds to one of the sets of first conductivity type transistors.
each of the plurality of first conductivity type transistors is connected in advance by a gate electrode layer, and further, another second conductivity type transistor in each of the plurality of sets of second conductivity type transistors corresponds thereto. The set of transistors of the first conductivity type is connected in advance to another transistor of the first conductivity type among the set of transistors of the first conductivity type adjacent to the set of transistors of the first conductivity type by respective other gate electrode layers. A featured master slice semiconductor integrated circuit device.