JPS6442183A - Method of packaging semiconductor device - Google Patents

Method of packaging semiconductor device

Info

Publication number
JPS6442183A
JPS6442183A JP19850887A JP19850887A JPS6442183A JP S6442183 A JPS6442183 A JP S6442183A JP 19850887 A JP19850887 A JP 19850887A JP 19850887 A JP19850887 A JP 19850887A JP S6442183 A JPS6442183 A JP S6442183A
Authority
JP
Japan
Prior art keywords
board
chip
transparent
parts
chip mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19850887A
Other languages
Japanese (ja)
Other versions
JP2532496B2 (en
Inventor
Yoshiko Mino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62198508A priority Critical patent/JP2532496B2/en
Publication of JPS6442183A publication Critical patent/JPS6442183A/en
Application granted granted Critical
Publication of JP2532496B2 publication Critical patent/JP2532496B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Led Devices (AREA)
  • Led Device Packages (AREA)

Abstract

PURPOSE:To facilitate packaging of chips accurately and facilitate batch processing of wirings between electrodes with every chip mounting board as a unit of processing by a method wherein recessed parts for absorbing the difference in chip thickness are provided in the chip mounting board and an evaporation wiring method or a printing wiring method is applied. CONSTITUTION:Ultraviolet and heat curing type resin is applied to the whole main surface of a board 1. After chips 3a and 3b are put in the recessed parts 2 of the board 1, a transparent board is put on the main surface of the board and a pressure is applied to the transparent board. Ultraviolet rays are applied to the resin through the transparent board with the transparent board fixed by pressure and, further, the resin in the parts where the ultraviolet rays can not reach is cured by heat. Then the transparent board is removed and, after an insulating film 9 is formed over the whole surface except electrode parts, electrode wirings 12 are formed by an evaporation method or a printing method. With this constitution, the chip mounting board which has the recessed parts absorbs the difference in chip thickness and the inclination of the chip and the step between the chip and the board produced at the time of die-bonding are corrected to keep the surface of the chip and the surface of the board in the same plane and the electrode wirings for mounting can be formed by batch processing with every chip mounting board as a unit of processing by utilizing an evaporation method or a printing method.
JP62198508A 1987-08-07 1987-08-07 Semiconductor device mounting method Expired - Fee Related JP2532496B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62198508A JP2532496B2 (en) 1987-08-07 1987-08-07 Semiconductor device mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62198508A JP2532496B2 (en) 1987-08-07 1987-08-07 Semiconductor device mounting method

Publications (2)

Publication Number Publication Date
JPS6442183A true JPS6442183A (en) 1989-02-14
JP2532496B2 JP2532496B2 (en) 1996-09-11

Family

ID=16392302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62198508A Expired - Fee Related JP2532496B2 (en) 1987-08-07 1987-08-07 Semiconductor device mounting method

Country Status (1)

Country Link
JP (1) JP2532496B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004184797A (en) * 2002-12-05 2004-07-02 Seiko Epson Corp Electronic device, method of manufacturing the same, and electronic device
JP2013093453A (en) * 2011-10-26 2013-05-16 Nippon Dempa Kogyo Co Ltd Electronic module and manufacturing method therefor
JP2017092092A (en) * 2015-11-04 2017-05-25 豊田合成株式会社 Method for manufacturing light emitting device
CN107833903A (en) * 2016-09-15 2018-03-23 伊乐视有限公司 Emissive display with light management system
CN111640708A (en) * 2020-06-22 2020-09-08 武汉华星光电半导体显示技术有限公司 Display module and its manufacturing method and electronic device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004184797A (en) * 2002-12-05 2004-07-02 Seiko Epson Corp Electronic device, method of manufacturing the same, and electronic device
JP2013093453A (en) * 2011-10-26 2013-05-16 Nippon Dempa Kogyo Co Ltd Electronic module and manufacturing method therefor
JP2017092092A (en) * 2015-11-04 2017-05-25 豊田合成株式会社 Method for manufacturing light emitting device
CN107833903A (en) * 2016-09-15 2018-03-23 伊乐视有限公司 Emissive display with light management system
CN111640708A (en) * 2020-06-22 2020-09-08 武汉华星光电半导体显示技术有限公司 Display module and its manufacturing method and electronic device
CN111640708B (en) * 2020-06-22 2022-08-05 武汉华星光电半导体显示技术有限公司 Display module, manufacturing method thereof and electronic equipment

Also Published As

Publication number Publication date
JP2532496B2 (en) 1996-09-11

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees