JPS6445400U - - Google Patents
Info
- Publication number
- JPS6445400U JPS6445400U JP14054587U JP14054587U JPS6445400U JP S6445400 U JPS6445400 U JP S6445400U JP 14054587 U JP14054587 U JP 14054587U JP 14054587 U JP14054587 U JP 14054587U JP S6445400 U JPS6445400 U JP S6445400U
- Authority
- JP
- Japan
- Prior art keywords
- operational amplifier
- fet
- input terminal
- offset voltage
- voltage adjustment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第１図乃至第２図はこの考案の実施例を示し、
第１図は要部の回路図、第２図はＦＥＴの動作点
を示す特性図、第３図は従来の実施例を示す回路
図である。
主要部分の符号の説明、１，５，７：抵抗器、
２：アナログスイツチ、３：ＦＥＴ、４：半固定
抵抗器、６：演算増幅器、８：コンデンサ。
Figures 1 and 2 show an embodiment of this invention,
FIG. 1 is a circuit diagram of the main part, FIG. 2 is a characteristic diagram showing the operating point of the FET, and FIG. 3 is a circuit diagram showing a conventional embodiment. Explanation of symbols of main parts, 1, 5, 7: resistor,
2: analog switch, 3: FET, 4: semi-fixed resistor, 6: operational amplifier, 8: capacitor.
Claims (1)
とこの演算増幅器の入力インピーダンスを高める
ために用いるＦＥＴバツフア増幅器とからなる位
相反転型サンプルホールド回路のオフセツト電圧
調整回路において、 前記ＦＥＴバツフア増幅器のＦＥＴのソースと
演算増幅器の反転入力端子との間、または、演算
増幅器の反転入力端子とマイナス電源との間に可
変出来る抵抗器を設けたことを特徴とするサンプ
ルホールド回路のオフセツト電圧調整回路。[Claims for Utility Model Registration] In an offset voltage adjustment circuit for a phase inversion type sample and hold circuit comprising a sampling analog switch, an operational amplifier, and a FET buffer amplifier used to increase the input impedance of the operational amplifier, the FET buffer amplifier comprises: An offset voltage adjustment circuit for a sample-and-hold circuit, characterized in that a variable resistor is provided between the source of the FET and the inverting input terminal of the operational amplifier, or between the inverting input terminal of the operational amplifier and the negative power supply. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14054587U JPH0422477Y2 (en) | 1987-09-14 | 1987-09-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14054587U JPH0422477Y2 (en) | 1987-09-14 | 1987-09-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6445400U true JPS6445400U (en) | 1989-03-20 |
| JPH0422477Y2 JPH0422477Y2 (en) | 1992-05-22 |
Family
ID=31404814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14054587U Expired JPH0422477Y2 (en) | 1987-09-14 | 1987-09-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0422477Y2 (en) |
-
1987
- 1987-09-14 JP JP14054587U patent/JPH0422477Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0422477Y2 (en) | 1992-05-22 |