JPS6448457A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6448457A
JPS6448457A JP62203981A JP20398187A JPS6448457A JP S6448457 A JPS6448457 A JP S6448457A JP 62203981 A JP62203981 A JP 62203981A JP 20398187 A JP20398187 A JP 20398187A JP S6448457 A JPS6448457 A JP S6448457A
Authority
JP
Japan
Prior art keywords
silicon
layer
silicon dioxide
region
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62203981A
Other languages
Japanese (ja)
Inventor
Shinji Nakamura
Itaru Namura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62203981A priority Critical patent/JPS6448457A/en
Publication of JPS6448457A publication Critical patent/JPS6448457A/en
Pending legal-status Critical Current

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Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To omit an etching process difficult to be controlled by a method wherein silicon is patterned to a specific shape by using a single mask, the single crystal and polycrystal of silicon are grown simultaneously, a post composed of silicon dioxide is removed, and a recessed section is formed in an intrinsic base forming region. CONSTITUTION:Silicon dioxide is patterned to a shape that there is a pots consisting of an silicon dioxide layer 7 at a central section, an intrinsic base region, on one conductivity type silicon layer 1, the n-type silicon layer 1 is exposed to an external base region and an silicon nitride layer 3 is laminated onto an silicon dioxide layer 2 in a region surrounding the external base region by employing a single mask. A single crystal silicon layer 9 and a polycrystalline silicon layer 10 are shaped respectively by executing the single crystal and polycrystal simultaneous growth method of silicon, and lastly the post made up of silicon dioxide 7 is removed, thus forming the intrinsic base forming region. Accordingly, only one alignment mask is sufficient, and an etching process difficult to be controlled is omitted.
JP62203981A 1987-08-19 1987-08-19 Manufacture of semiconductor device Pending JPS6448457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62203981A JPS6448457A (en) 1987-08-19 1987-08-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62203981A JPS6448457A (en) 1987-08-19 1987-08-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6448457A true JPS6448457A (en) 1989-02-22

Family

ID=16482819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62203981A Pending JPS6448457A (en) 1987-08-19 1987-08-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6448457A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000017932A1 (en) * 1998-09-21 2000-03-30 Institut für Halbleiterphysik Frankfurt (Oder) GmbH Bipolar transistor and method for producing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000017932A1 (en) * 1998-09-21 2000-03-30 Institut für Halbleiterphysik Frankfurt (Oder) GmbH Bipolar transistor and method for producing same

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