JPS6450431U - - Google Patents
Info
- Publication number
- JPS6450431U JPS6450431U JP1987145458U JP14545887U JPS6450431U JP S6450431 U JPS6450431 U JP S6450431U JP 1987145458 U JP1987145458 U JP 1987145458U JP 14545887 U JP14545887 U JP 14545887U JP S6450431 U JPS6450431 U JP S6450431U
- Authority
- JP
- Japan
- Prior art keywords
- electrode structure
- wiring layer
- passivation film
- aluminum wiring
- bonding part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/981—Auxiliary members, e.g. spacers
- H10W72/983—Reinforcing structures, e.g. collars
Landscapes
- Wire Bonding (AREA)
Description
第1図はこの考案の1実施例にかかる電極構造
の断面図、第2図は第1図に示す装置の動作説明
図、第3図はこの考案の第2の実施例の断面図、
第4図はこの考案の従来例の断面図、第5図は第
4図に示す装置の動作説明図である。 1……シリコン半導体基体、3……アルミ配線
層、4……ワイヤ、5……パツシベーシヨン膜、
7……多結晶シリコン配線層、9……拡散層。
の断面図、第2図は第1図に示す装置の動作説明
図、第3図はこの考案の第2の実施例の断面図、
第4図はこの考案の従来例の断面図、第5図は第
4図に示す装置の動作説明図である。 1……シリコン半導体基体、3……アルミ配線
層、4……ワイヤ、5……パツシベーシヨン膜、
7……多結晶シリコン配線層、9……拡散層。
Claims (1)
- 半導体基体上に形成したアルミ配線層を、ワイ
ヤとのボンデイング部を除いてパツシベーシヨン
膜で保護した半導体素子の電極構造において、上
記アルミ配線層の下の上記ボンデイング部からパ
ツシベーシヨン膜に至る領域に対応する部分に耐
腐食性の導電層を設けたことを特徴とする半導体
素子の電極構造。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987145458U JPS6450431U (ja) | 1987-09-25 | 1987-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987145458U JPS6450431U (ja) | 1987-09-25 | 1987-09-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6450431U true JPS6450431U (ja) | 1989-03-29 |
Family
ID=31414067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987145458U Pending JPS6450431U (ja) | 1987-09-25 | 1987-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6450431U (ja) |
-
1987
- 1987-09-25 JP JP1987145458U patent/JPS6450431U/ja active Pending