JPS6452142A - Pattern forming process and silylating apparatus - Google Patents

Pattern forming process and silylating apparatus

Info

Publication number
JPS6452142A
JPS6452142A JP62209557A JP20955787A JPS6452142A JP S6452142 A JPS6452142 A JP S6452142A JP 62209557 A JP62209557 A JP 62209557A JP 20955787 A JP20955787 A JP 20955787A JP S6452142 A JPS6452142 A JP S6452142A
Authority
JP
Japan
Prior art keywords
film
substrate
resist
plasma
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62209557A
Other languages
Japanese (ja)
Inventor
Yoshiaki Mimura
Isamu Odaka
Masanobu Doken
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62209557A priority Critical patent/JPS6452142A/en
Publication of JPS6452142A publication Critical patent/JPS6452142A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/36—Imagewise removal not covered by groups G03F7/30 - G03F7/34, e.g. using gas streams, using plasma
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H10P76/2043—Photolithographic processes using an anti-reflective coating

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To obtain a precise pattern by hardening a resist film by bringing a substrate into contact with an org. silane after exposure and development of the resist, then removing unnecessary reflection preventing film remaining on the substrate by decomposing the film with gaseous O2 plasma thereafter. CONSTITUTION:A substrate having a photosensitive film thereon is formed by coating the substrate with a reflection preventing film and a resist film. A resist pattern is formed by exposing the substrate and carrying out resist development. Then, in a stage 1, the substrate is heated and brought into contact with a soln. or vapor of an organosilane (dimethyl chlorosilane, etc.). In this stage, the resist film is hardened by a silylating reaction by irradiating the film with far-ultraviolet rays. By this treatment, resistance to O2 plasma is imparted to the resist film of a pattern. Then, in the second stage 2, the substrate is exposed to O2 plasma to remove the reflection preventing film remaining on the substrate other than the resist pattern by decomposing the film with O2 plasma. Since resistance to O2 plasma is imparted to the resist film by the silylating reaction, a fine pattern having high precision is obtd.
JP62209557A 1987-08-24 1987-08-24 Pattern forming process and silylating apparatus Pending JPS6452142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62209557A JPS6452142A (en) 1987-08-24 1987-08-24 Pattern forming process and silylating apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62209557A JPS6452142A (en) 1987-08-24 1987-08-24 Pattern forming process and silylating apparatus

Publications (1)

Publication Number Publication Date
JPS6452142A true JPS6452142A (en) 1989-02-28

Family

ID=16574793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62209557A Pending JPS6452142A (en) 1987-08-24 1987-08-24 Pattern forming process and silylating apparatus

Country Status (1)

Country Link
JP (1) JPS6452142A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02250006A (en) * 1989-03-24 1990-10-05 Fujitsu Ltd Method for peeling resist
WO1996019753A1 (en) * 1994-12-19 1996-06-27 Advanced Micro Devices, Inc. Selective i-line barl etch process
US5763327A (en) * 1995-11-08 1998-06-09 Advanced Micro Devices, Inc. Integrated arc and polysilicon etching process
US5795829A (en) * 1996-06-03 1998-08-18 Advanced Micro Devices, Inc. Method of high density plasma metal etching
US5807790A (en) * 1996-05-07 1998-09-15 Advanced Micro Devices, Inc. Selective i-line BARL etch process
US6025268A (en) * 1996-06-26 2000-02-15 Advanced Micro Devices, Inc. Method of etching conductive lines through an etch resistant photoresist mask
US6316168B1 (en) * 1999-04-12 2001-11-13 Siemens Aktiengesellschaft Top layer imaging lithography for semiconductor processing
KR20200104234A (en) * 2019-02-26 2020-09-03 도쿄엘렉트론가부시키가이샤 Method of line roughness improvement by plasma selective deposition

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6225424A (en) * 1985-07-26 1987-02-03 Nippon Telegr & Teleph Corp <Ntt> Pattern forming method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6225424A (en) * 1985-07-26 1987-02-03 Nippon Telegr & Teleph Corp <Ntt> Pattern forming method

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02250006A (en) * 1989-03-24 1990-10-05 Fujitsu Ltd Method for peeling resist
WO1996019753A1 (en) * 1994-12-19 1996-06-27 Advanced Micro Devices, Inc. Selective i-line barl etch process
US5763327A (en) * 1995-11-08 1998-06-09 Advanced Micro Devices, Inc. Integrated arc and polysilicon etching process
US5885902A (en) * 1995-11-08 1999-03-23 Advanced Micro Devices, Inc. Integrated arc and polysilicon etching process
US5807790A (en) * 1996-05-07 1998-09-15 Advanced Micro Devices, Inc. Selective i-line BARL etch process
US5795829A (en) * 1996-06-03 1998-08-18 Advanced Micro Devices, Inc. Method of high density plasma metal etching
US6025268A (en) * 1996-06-26 2000-02-15 Advanced Micro Devices, Inc. Method of etching conductive lines through an etch resistant photoresist mask
US6316168B1 (en) * 1999-04-12 2001-11-13 Siemens Aktiengesellschaft Top layer imaging lithography for semiconductor processing
KR20200104234A (en) * 2019-02-26 2020-09-03 도쿄엘렉트론가부시키가이샤 Method of line roughness improvement by plasma selective deposition
US11537049B2 (en) * 2019-02-26 2022-12-27 Tokyo Electron Limited Method of line roughness improvement by plasma selective deposition

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