JPS6474754A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6474754A JPS6474754A JP62233283A JP23328387A JPS6474754A JP S6474754 A JPS6474754 A JP S6474754A JP 62233283 A JP62233283 A JP 62233283A JP 23328387 A JP23328387 A JP 23328387A JP S6474754 A JPS6474754 A JP S6474754A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- sio2
- temperature
- impurity
- prebaked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To obtain an excellent step coverage and prevent the disconnection and the migration of an Al wiring by a method wherein an interlaminar insulating film, which impurity is diffused and is leveled through the intermediary of a P-type or an N-type impurity diffusion material layer, is provided. CONSTITUTION:A semiconductor layer 103 is deposited on an insulating substrate 1, a SiO2 layer 104 is made to grow thereon by heating, and furthermore a polysilicon layer 105 is formed thereon. PSG is applied thereon through a spin coating method or a dipping method, which is prebaked in an active gas atmosphere at a temperature lower than the temperature that the impurity starts to diffuse. A process follows, where a SiO2 layer is applied and pre-baked. The exposed SiO2 layer and a PSG layer 61 thereunder are removed through etching, a resist R is made to be separated, then BSG is applied on the whole face and prebaked. Furthermore, SiO2 film 8' is deposited on a BSG layer 62 through an LP-CVD method. And, a heat treatment is performed at a temperature of 600-1200 deg.C. By these processes, a leveled interlaminar insulating film can be obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62233283A JPS6474754A (en) | 1987-09-17 | 1987-09-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62233283A JPS6474754A (en) | 1987-09-17 | 1987-09-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6474754A true JPS6474754A (en) | 1989-03-20 |
Family
ID=16952668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62233283A Pending JPS6474754A (en) | 1987-09-17 | 1987-09-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6474754A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6335541B1 (en) | 1993-10-29 | 2002-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor thin film transistor with crystal orientation |
| JP2017034263A (en) * | 2011-06-10 | 2017-02-09 | 株式会社半導体エネルギー研究所 | Manufacturing method of semiconductor device |
-
1987
- 1987-09-17 JP JP62233283A patent/JPS6474754A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6335541B1 (en) | 1993-10-29 | 2002-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor thin film transistor with crystal orientation |
| US6998639B2 (en) | 1993-10-29 | 2006-02-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device |
| US7998844B2 (en) | 1993-10-29 | 2011-08-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device |
| JP2017034263A (en) * | 2011-06-10 | 2017-02-09 | 株式会社半導体エネルギー研究所 | Manufacturing method of semiconductor device |
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