JPS6480034A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS6480034A
JPS6480034A JP62234944A JP23494487A JPS6480034A JP S6480034 A JPS6480034 A JP S6480034A JP 62234944 A JP62234944 A JP 62234944A JP 23494487 A JP23494487 A JP 23494487A JP S6480034 A JPS6480034 A JP S6480034A
Authority
JP
Japan
Prior art keywords
lead frame
lead
integrated circuit
semiconductor integrated
frame pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62234944A
Other languages
Japanese (ja)
Inventor
Kazumi Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62234944A priority Critical patent/JPS6480034A/en
Publication of JPS6480034A publication Critical patent/JPS6480034A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/701—Tape-automated bond [TAB] connectors

Landscapes

  • Connector Housings Or Holding Contact Members (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To expand a region in which a lead frame pattern can be formed, by forming in each partition of a lead frame a lead frame pattern to be connected only to the terminal placed on one side of a semiconductor integrated circuit. CONSTITUTION:On lead frames 8, 9, first and second lead frame patterns 2, 5 are respectively formed, and the respective lead frames 8, 9 are arranged radially with their device holes 4 being matched each other. And, a semiconductor integrated circuit 7 is placed in the rectangular region formed of the four device holes 4, and by connecting a bump 10 placed in each side of the semiconductor integrated circuit 7 and the lead of each lead frame pattern 2, 5, the semiconductor integrated circuit 7 is mounted on the lead frames. That is, the lead frame pattern provided in each partition of the lead frames is a pattern corresponding to each side.
JP62234944A 1987-09-21 1987-09-21 Lead frame Pending JPS6480034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62234944A JPS6480034A (en) 1987-09-21 1987-09-21 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62234944A JPS6480034A (en) 1987-09-21 1987-09-21 Lead frame

Publications (1)

Publication Number Publication Date
JPS6480034A true JPS6480034A (en) 1989-03-24

Family

ID=16978714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62234944A Pending JPS6480034A (en) 1987-09-21 1987-09-21 Lead frame

Country Status (1)

Country Link
JP (1) JPS6480034A (en)

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